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Where To Find This Example

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Design Notes


This project demonstrates the design of a 16-Way Wilkinson microstrip power divider. The divider uses multiple stages of a four-section Wilkinson two-way divider. The MTRACE2 element is used for almost all of the transmission line sections, which allows complex layouts to be created and accurately simulated with a simple schematic representation.

Simulation Details

The schematic "Four_Section_Ideal_Divider" shows the design of an ideal Wilkinson divider to demonstrate the achievable bandwidth with multiple sections.

The transmission lines are ideal and lossless, and the resistors are lumped. Note the line impedances drop from the first to the last sections, as the resistor values increase.

The schematic "Four_Section_MS_Divider" shows a microstrip implementation of the ideal divider. 

The quarter-wave lines are modeled with MTRACE2 elements, which allow the designer to create the desired layout graphically by adding bends and stretching segments of the trace in the layout view. Because the AWR Design Environment uses a single database for layout and simulation, the electrical model of the MTRACE2 is automatically updated as the user adds bends and line segments to the layout. When simulated, all these elements are accounted for, and the result is the same as if the user had placed individual MLINs and MBENDS in the schematic.

The layout of the divider is kept symmetric with another powerful feature of the AWR Design Environment: the parameters of one element can be derived from another. For example, as the MTRACE2 of one quarter-wave section is stretched; the arm on the other side of the isolation resistor mirrors it exactly. This is true during tuning or optimizing as well. To see how this is done, bring up the Element Options dialog by double-clicking on the schematic symbol for MTRACE2.X2 (in the first section of the divider, on the bottom half of the schematic.) Click on the 'Show Secondary' button. Note that the parameters W, L, DB, and RB use the syntax W@MTRACE2.X1, L@MTRACE2.X1, etc, which means that they are set equal to the same variables in MTRACE2.X1.

The schematic "16_Way_Power_Divider" uses the same techniques as the "Four_Section_MS_Divider" to create a detailed layout with a relatively simple schematic.

The lines connecting the "Four_Section_Ideal_Divider" sub-circuits are all symmetric, deriving their parameters from the top-most MTRACE2 in each stage.

Training Exercise

For further help on editing TRACE elements, please review the chapter on Layout in the MWO/AO User Guide.

Tuning and Optimization

This project has been setup for tuning and optimization of the "Four_Section_MS_Divider" design. The frequency steps for this schematic have been set at 1GHz for faster simulations. For finer resolution on the Four Section Microstrip Divider graph, change the frequency steps on the corresponding schematic to 0.1GHz.

Bring up the Optimizer (F7) and click on the variables tab to see the list of optimization variables.

Run the tuner to see the results on the "Four Section Microstrip Divider" graph and notice that the layout is also updating.    Try changing values with the tuner and then use the optimizer to see if you can get the circuit performance back to the optimized state.  


In order to achieve more accurate results, you can enable the EXTRACT block in the Four_Section_MS_Divider schematic.  This will send the four-section layout to the Axiem EM simulator for EM analysis.