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AWR MMIC MODULE
This project demonstrates the use of extraction to simulate mixed technology design. Analyst extraction is used to simulate the MMIC-bond wire-board transition. AXIEM extraction is used to simulate MMIC components. ACE is used to simulate iNet traces on the board. Analyst, AXIEM, and ACE licenses are required to run the respective extraction simulations.
This project shows the design of a 2.5 GHz PA created using the combination of the AWR GaAs MMIC process and the 4-layer AWR Module process - utilizing the multiple-process capabilities of the NI AWR Design Environment. The final design has about 9.5 dB gain and 1/4 Watt output power at 1dB compression.
In this schematic, we have created a single-stage, GaAs MMIC amplifier with bias control.
This schematic uses a different LPF and STACKUP from the top level module schematic. The amplifier MMIC has no output matching on the chip, so load pull analysis is used determine the best output match for optimum output power.
Analyst Extraction is used to simulate the transition between the MMIC and module. In the “1stage_Amp” schematic, the bond pads are enabled for Analyst Extraction, using the group name specified in the EXTRACT block in that schematic. This same group name is used by another EXTRACT block in the top level schematic “Packaged_Amp”. By sharing group names, the MMIC bond pads are extracted as an EM subcircuit, utilizing a different STACKUP than the top level extracted EM structure.
The remaining circuitry in “1stage_Amp” is extracted using AXIEM. The EXTRACT block controlling the AXIEM extraction is located in the “Packaged_Amp” schematic.
This bench allows the user to find the optimum output match for the MMIC amplifier using the new Load Pull Script (Scripts > Load Pull > Load Pull). Once the optimum load pull point is determined, as shown on the “Load Pull” graph, we can begin design of the off-chip output match.
A very basic shunt-capacitor output match circuit was created to optimize the output power for the amplifier.
In the output match layout, iNets were simulated using ACE (Automated Circuit Extraction). The extraction is controlled by the EXTRACT block in the “Packaged_Amp” schematic. The value of the shunt capacitor was then fine-tuned to match the optimum impedance value given in the “Load Pull” graph.
A Bond pad in this schematic is also selected for Analyst Extraction. Since this schematic uses the same STACKUP and LPF as the top level schematic, no extra EXTRACT block for Analyst Extraction is necessary in this schematic.
Both the MMIC and module schematics were combined in this schematic.
Bond wires are used to connect between the MMIC and board subcircuits. The bond wires are also selected for Analyst Extraction. “Packaged_Amp” schematic is the top level circuit, so Extract blocks for Analyst, AXIEM, and ACE are located in this schematic. Because this circuit is placed in a test bench (“Power_Sweep”), Hierarchy=On is set for all Extract blocks, since measurements are made on the test bench, and not this schematic. Enable the Extract blocks to compare circuit versus EM simulation results.
“Power_Sweep” is a test bench used to perform swept power analysis on the complete amplifier module. The input power is swept from 0 to 17 dBm. The amplifier's performance is shown in the “Gain vs Output Power” and “Waveforms” graphs.