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Design Notes

"Tweaking" Line Lengths after EM Simulation

This project shows how to extract a transmission line for EM simulation, such that its length can then be tuned without re-extraction.

Overview

EM Extraction allows designers to conveniently verify the performance of collections of elements using an EM simulator.  If a microstrip line is simply included in the extraction, there is no way to take advantage of the EM results, AND quickly tune or optimize that line's length. 

This project shows two techniques for adding electrical length to an extracted microstrip line, so that it can be tuned or optimized without changing the line's physical shape in layout, and avoid re-extraction and a new EM simulation with each change.  Once the correct length is found, the additional electrical length model can be removed, and the original line's length can be adjusted physically as needed, so that a new extraction can verify the desired performance has been acheived.

PDK

The Microwave Office PDK used in this project is the AWR_MESFET which provides an AXIEM specific STACKUP called "Thick Metal". 

Modeling and Simulation

The two techniques described here apply to two different cases:

• The added length of line is "short" and can be reasonably modeled  without shunt elements; e.g. modeled using series L or RL.

• The added length is longer than half of the substrate height (H/2).

Short Line

The schematic "Internal_Port_Inductor_Approach"  is primarily just a microstrip line, which is extracted for simulation with AXIEM.  There is also an additional set of elements in the box named "Tweakers": an ideal lumped inductor whose value is set in Global Definitions, connected between a LOAD element and ground.  The LOAD element is not used as an electrical model and has it's layout set to be an MLEF.  It acts as a place-holder for the internal port to be added in the layout.  It matches the width and line type of the microstrip line, is placed so it overlaps a short segment of the line, and an AXIEM extraction port is attached to its face (select the MLEF's layout cell, Draw > Extraction Port, and click on the edge corresponding to the port).  The extraction port is then edited (double-click) to set its Explicit Ground Reference to Internal_port.

After extraction the inductor in the schematic will effectively be connected in series with the line at the point where the extraction port is inserted in the layout.  The inductor's value can be adjusted to effectively add length to the extracted line.  Use the Tuner to vary the "TwkInd" variable (set in Global Definitions) to see its effect.  Once the appropriate inductance value is determined for desired overall performance, the next step is to find the equivalent length to add to the line. 

The "Tweak_Inductor" schematic contains only an inductor with the same value as above, assumed to be the desired value.  The "Tweak_Line" schematic is a microstrip line (ID=EqLn) with the same width as the extracted line, whose length is to be tuned or optimized to match the delay of the inductor.  The "Short Line vs Inductor Delay" and "Short Line vs Inductor Phase Difference" graphs compare the "Tweak_Inductor" and "Tweak_Line" schematics.  Optimization has already been setup to vary the length of EqLn in order reduce the phase difference measurement to near zero.

Internal ports have the advantage of adding only one port to the EM structure, but allowing the addition of a series element.  There is a restriction, however: the series element must not conduct current anywhere but between the two terminals.  For example, a long microstrip line is inappropriate, because it has a significant capacitive connection to ground.

Long Line (L > H/2)

The schematic "mutual_port_approach" shows a 450um microstrip line (MLIN) divided into 3 series segments: a 50um segment between two 200um segments. These lines were originally "snapped together" in the layout.  In the schematic, a (tweaker) copy of the 50um segment is connected in parallel with the original, and the original is disabled.  The properties for the tweaker line have been edited to set its layout to None; so it does not appear in, or affect the layout.  Extraction ports are added to the ends of the gap formed in the layout by the missing line, and the extraction ports' properties are edited to make them a Mutual port group with the lower plane as their explicit ground.

After EM simulation, the length of the tweaker MLIN can be tuned or optimized to determine the value that acheives the desired simulation results.  Then both of the parallel lines in the schematic can be selected, right-click > Toggle Enable to return to the orignal circuit; the length of the original MLIN can be edited as necessary, and the layout re-arranged to accomodate the change.

Add the gap to a section of the line where it is least likely to couple with anything else.  If the lenght of a coupled pair of lines needs to be varied, then add the gap to both lines, adjacent to each other, and use a coupled line electrical model for the tweaker.

Simulation Plots

"Phase Delay of Complete Lines" shows the angle of S21 for the complete lines in both approaches; i.e. for the extracted line(s) and the added tweaker delay. 

"Short Line vs Inductor Delay" shows the phase for the tweaker inductor, and that of the line length by which it is to be replaced, for comparison.

"Short Line vs Inductor Phase difference" shows the difference in phase delay between the same inductor and line.  Optimization goals are added to bring this difference to near zero degrees.  The line length parameter, L, will be optimized to make the delays match each other.

Schematic - Mutual_Port_Approach

Schematic - Internal_Port_Inductor_Approach

Schematic Layout - Internal_Port_Inductor_Approach

Graph - Phase Delay of Complete Lines