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Balanced Amplifier Design
This example is an 8 to 10 GHz amplifier design using two NEC N76038A devices configured in a balanced configuration. The technology used is a mix of a thin film process for the resistors and chip components for capacitors. The substrate used is 25 mil thick alumina.
The purpose of this example is to demonstrate setting up AWR for a generic process technology; the performance of this amplifier is not the main focus of the example. An application note on our Knowledge Base (<http://www.awrcorp.com/support/>) titled “Balanced Amplifier Layout Application Note - Detailed Layout Application Note” takes you from a blank AWR project with no layout configured and ends with this layout and simulation. This is an excellent resource for learning how to properly use AWR for configuring different process technologies and how to do many different tasks using layout.
The basic principle used in this design was to build a balanced structure to help get good broadband match and gain from this circuit. The “Prematch” schematic is the device and some basic matching elements.
You can see the “Pre_Match”
and “Pre_Match Smith”
graphs to see the matching for this part of the design.
Then a Wilkinson divider is used to split the input signal and continue down 50 ohm lines to the two pre-matched sections.
The difference in length to the input of each pre-match section is set to an electrical length of 90 degrees. Any reflected signals will be 180 degrees out of phase and cancel each other out, thus improving the overall performance of the circuit. Please see the “Balanced Amplifier Response"
and “Smith Balanced Amplifier Response”
graphs to see how this balanced structure improves the overall match and gain of the circuit.
The top level Schematic "Balanced_Amplifier" contains the subcircuit "Wilkinson" which is designed using EM Extraction. In other words, an EM model of the schematic is generated from the schematic layout. Notice there is no EM structure in this project when first opened, but one is generated when the project is simulated.
The extraction process is controlled by the Extract Block. The Hierarchy parameter determines how the schematic is extracted with respect to circuit hierarchy. If Hierarchy = On, then the schematic will be extracted at its current level, and the EM model will be used as a subcircuit in higher levels. Conversely, if Hiearchy = Off, the schematic will instead be included as part of the extraction at the higher levels.
On the Extract Block in "Wilkinson", Hierarchy = On. Thus, it is extracted at the subcircuit level to EM Doc "EM_Wilkinson". There are two instances of "Wilkinson" in the top level schematic "Balanced_Amplifier", however, the EM simulation of "Wilkinson" is only analyzed once at the subcircuit level, and the results are used twice as a subcircuit.
Please refer to the graphs in the “Wilkinson” Folder for a comparison between the EM Extracted and Schematic results.
There is also an EXTRACT block in the top-level schematic. This can be enabled to extract the RF traces of the balanced amplifier to AXIEM for increased simulation accuracy.
For further help on Extraction, and more details on the setup, please review the online Users Guide on Extraction.
This design uses quite a few advanced capabilities that many users may not be aware of. They won’t be covered in detail here since they are covered in the application note. Some of the advanced techniques used are:
1. Cell stretcher for the thin film resistor layout cells. A cell stretcher is a way to make a simple parameterized layout cell using an artwork cell.
2. Intelligent element syntax for the Wilkinson schematic. This syntax is where one element can be assigned the same parameters as another element. This is different than using equations and is very useful for easily making symmetric structures.
3. Extensive use of the MTRACE2 elements. Notice the relative simple schematics used to generate all the microstrip lines and bends.
4. Equations were used to adjust the difference in electrical length to each path of the circuit so they will match on the input and output. Find the equation called “delta” in this project and tune on that element (this is already set up). Notice the change in the circuit results and layout as you tune this variable.