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Design Notes

LNA Design Template

Balanced amplifier eval board design template.  This project shows design methodolgy for making a 2.4 GHz  - 2.6 GHz balanced LNA using an NEC52418 low noise HBT transistor.  The methodolgy shown is "portable" and could be used for any device type, or to create different eval boards for several different devices.

Balanced Amplifier Design goals (2.4 - 2.6 GHz):

• Ic < 10 mA

• Vcc = 5 V

• S11 and S22 < -15 dB

• Gain > 15 dB

• OIP3 > 15 dBm

• Noise Figure < 2.0 dB

Single stage design goals derived from these specifications (2.4 - 2.6 GHz):

• Ic < 5 mA (half current for each device)

• Vcc = 5 V

• S11 and S22 < -12 dB (balanced design will improve this)

• Gain > 15 dB (balanced design will not improve this)

• OIP3 > 15 dBm (balanced design will not improve this)

• Noise Figure < 1.5 dB (balanced design will degrade this)

Imported data files for LNA device:

• SPICE (nonlinear) models are imported in the "Circuit Schematics" section of the "Project" tab.  Often when importing spice models for active devices a warning will be given about swapping the pin order - Choose either "Yes" or "No" and then look at the DCIV curves.  If the curves are not correct then delete the circuit, re-import it, and choose yes.

• S-parameter files should be imported and left under the "Data Files" section of the "Project" tab.

Items to note about design:

• The system and circuit schematics (and design steps) are described below.  The system schematics are designed to have been used first to determine the LNA specs and then lastly to validate that the design works in the system as expected.

• AXIEM was used to calculate the response of the "Quarter_Wave_Line." 

• The different representations of the Quarter_Wave_Line structure can be compared by looking at the "Quarter Wave Insertion Loss," "Quarter_Wave_Line S11," and "Quarter Wave Phase" Graphs.  The line was simulated as an MTRACE, and AXIEM Structure. There are three graphs that compare the gain and match of the final balanced design by simulating with MWO Linear and MWO Non-linear (small signal input).  To view these results, see the graph "6b Gain Linear vs HB," "6b S11  Linear vs HB," and "6b S22 Linear vs HB." 

• To view the stability analysis results, the measurements under the "7 Load Pull Values" and "7 Stability Load and Source Pull" Graphs must be enabled.  Note that it is simulating 1296 points and takes ~10 seconds to run.  It's clear from the results that the design is very unstable at most loads around the edge of the smith chart.  The on the global variable "AngState" to step through the "Load Angle" values (all Source Angles are plotted) and see the corresponding results.

Final Design Performance (2.4 - 2.6 GHz):

• Ic = 9.6 mA

• Vcc = 5 V

• S22 < -17 dB (S11 < -12 dB, matched for noise)

• Gain(min) > 14.5 dB

• OIP3 > 16 dBm

• Noise Figure(max) < 1.6 dB

Circuit Schematics

1_Generate DCIV Curves

Look at DCIV curves of the nonlinear model.  Make sure the curves look approriate for the device type.  Set up DC sweep so that Ic and Vc will be similar to the bias conditions for the s-parameter file.

2_Compare_SPICE and_S2P

Ensure that SPICE model is valid by comparing to vendor provided s-parameters. Place an instance of the SPICE model in the "Nonlinear_Transistor" circuit schematic.  Heirarchy allows this same circuit to be used throughout the design.  Use the DCIV data to get close to the necessary Ib (or Vb) values and then tune the bias supply to match the Ic and Vc operating condidtions in the different s-parameter files.  Compare the SPICE model to the S-parameter model with the "SModel" measurement.  The two models should align well.


Choose an operating point that gives best performance while meeting specifcations above for a single stage. Tune SPICE model bias supply to match bias conditions of the s-parameter files.  Operating point is picked based on design goals above.  For this device, GMax doesn't seem to change much with Ic (and is sufficient) so that's not a factor.  NFmin and IIP3 are affected by the bias, which is restricted by the Ic specification.  Choose Ic = 5 mA, which gives NFmin ~ 0.9 dB and IIP3 ~ 1.5 dBm.

3a_Device Load Pull

Gain and Noise figure load and source pull circles.


Use optimizer to solve for bias network values. For Ic = 5 mA and Vc = 2 V, Ib ~ 36 uA.  The Vcc available is 5 V.  Rc = (5V - 2V)/(5 mA) = 600 Ohms.  Set Rc to realistic value (based on "RArray) in "Passive_Bias_RC" schematic.  Again, heirarchy is used so that this value only has to be set in one place and can be used throughout the design.  Setting R1 and R2 is more difficult, as Vbe is unknown at this time.  Use optimizer to solve for the values to make Ib = 36 uA and verify that Ic = 5 mA.  Manually set R1 and R2 to realistic values.


Design the single stage LNA and matching network.  Place an instance of the correct s-parameter file (Ic = 5 mA, Vc = 2 V) in the "Linear_Transistor" subcircuit.  Hook the emitter to ground according to the planned board layout and verify that the layout for the device is correct.

Look at  S11, S12, S21, S22, Noise, and Stability while tuning or optimizing the single stage.  Keep in mind the single stage specifications mentioned above.  Verify OIP3 after tuning.

For more insight into the circuit, look at "5a Input Tuning" and "5b Output Tuning" graphs.  These graphs show the impedance that the matching circuit is presenting to the transistor and the conjugate of the impedance the transistor presents to the matching circuit while it is loaded with the actual circuit.  For maximum power transfer, these two numbers should like on top of one another.  Other considerations are match for best noise figure and regions of instability - both of these are also shown on the graphs. 

The layout shows the layout for one half of the balanced amplifier.


Transistor collector terminated with the output match.  Used to calculate S11 and Gamma Opt data for "5a Input Tuning" graph.


Transistor base terminated with the input match.  Used to calculate S22 data for "5b Output Tuning" graph.


Stability probes placed in-line to monitor transistor stability.  More information can be found in Appendix C of the Microwave Office User's Guide.


Combine two single stage layouts to create a balanced design. The "Wilkinson_Divider" schematic is fully parameterized, so the size (and shape) of the divider can be tuned to meet board size requirements.

The "Quarter_Wave_Line" schematic is an MTRACE, so can be drawn any shape to meet board size requirments. 

Two bias networks are used as instead of combining them, as this is just an eval board design and it saves design time to leave it this way.

Some tuning or optimization is necessary for the matching networks to center the balanced design.  Look at  S11, S12, S21, S22, Noise, and Stability while tuning or optimizing the balanced design.  Keep in mind balance specifications mentioned above.  Verify IIP3 after tuning.

This schematic contains the final layout of the board.


Calculate the IIP3 of the balanced amplifier.


Schematic setup for calculating large single s-parameters with Port 1 as a source and Port 2 as a termination.


Schematic setup for calculating large single s-parameters with Port 2 as a source and Port 1 as a termination.


Using the stability probes, perform a load/source pull on the device to ensure that no matter load is presented that the design remains stable.  More information about the stability probes can be found in Appendix C of the Microwave Office User's Guide.

Enable all the measurements under the "7 Load Pull Values" and "7 Stability Load and Source Pull" Graphs to see this simulation.  Note that it is simulating 1296 points and takes ~20 seconds to run.


Dummy circuit to graphically collect / display the load and source pull values used in "7 Device Stability Load and Source Pull".


Copy of the balanced amplifier with nonlinear transistor model from schematic "6a_Balanced_IIP3".  Source has been changed to single tone swept power source for generating a nonlinear behavioral model used in complex envelope system simulations.


Behavioral filter used to emulate front end filter for the LNA.  Used to generate a linear behavioral model used in complex envelope system simulations.

System Design

8c Behavioral System Simulation - System analysis (BER predictions) using nonlinear behavioral model.  This is the kind of budget simulation that often contributes to the LNA specifications.  Note the use of the "circuit level" behavioral filter.

8d Nonlinear System Simulation - System verification (BER predictions) using nonlinear model generated from the nonlinear balanced LNA subcircuit.  This setup verifies that the circuit design behaves in the system as well or better than the amplifier specified in "8c Behavioral System Simulation."