Page tree
Skip to end of metadata
Go to start of metadata

Where To Find This Example

Select Help > Open Examples... from the menus and type either the example name listed above or one of the keywords below.

Or in Version 13 or higher you can open the project directly from this page using this button. Make sure to select the Enable Guided Help before clicking this button.

Design Notes

Clock and Data Recovery (CDR) PLL and Phase Detectors

This project demonstrates three types of phase detectors used in a clock and data recovery (CDR) phased locked loop (PLL) circuit application, namely the Hogge, Alexander, and Meghelli [1-3] detectors. The bang-bang PLL operation is described in [4].

The phase detectors can be selected by double clicking on the 'PD Subsystem' SUBCKT and selecting from the drop down list in the 'PD_Type' field.

One can monitor the error signals, waveforms, spectrums, and the phase aligned data in the graphs.


Note the recovered 'Clock' and the 'Retimed Data' at the test points.

[1] C.R. Hogge, IEEE J. Lightwave Tech., pp. 1312-1314, 1985.

[2] J.D.H. Alexander, IEE Electronics Letters, pp. 541-542, 1975.

[3] M. Meghelli, et al., ISSCC 2000, pp. 56-57.

[4] R.C. Walker, et al., IEEE Journal of Solid-State Circuits, V. 27, N. 12, Dec. 1992.

System Diagram - Meghelli PD

System Diagram - Hogge PD

System Diagram - Alexander PD

System Diagram - System Diagram 1

Graph - Error

Graph - Waveforms

Graph - Data

Graph - Spectrum