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Clock and Data Recovery (CDR) PLL and Phase Detectors
This project demonstrates three types of phase detectors used in a clock and data recovery (CDR) phased locked loop (PLL) circuit application, namely the Hogge, Alexander, and Meghelli [1-3] detectors. The bang-bang PLL operation is described in .
The phase detectors can be selected by double clicking on the 'PD Subsystem' SUBCKT and selecting from the drop down list in the 'PD_Type' field.
One can monitor the error signals, waveforms, spectrums, and the phase aligned data in the graphs.
Note the recovered 'Clock' and the 'Retimed Data' at the test points.
 C.R. Hogge, IEEE J. Lightwave Tech., pp. 1312-1314, 1985.
 J.D.H. Alexander, IEE Electronics Letters, pp. 541-542, 1975.
 M. Meghelli, et al., ISSCC 2000, pp. 56-57.
 R.C. Walker, et al., IEEE Journal of Solid-State Circuits, V. 27, N. 12, Dec. 1992.