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Design Notes

CIC Decimator Filter

Cascaded Integrator-Comb (CIC) filters are designed to efficiently perform decimation or interpolation of digital signals.  They provide a flexible, multiplier-free architecture, which is suitable for hardware implementation and can also handle arbitrary and large rate changes.

This example demonstrates a CIC decimator filter, built out of N=4 integrator sections, a decimator by R=25, and N comb sections with differential delay M=1.  This design is based on the paper mentioned below [1].

The input sample rate is set to 6 MHz, resulting in a sampling rate of 240 kHz at the output of the decimator circuit.  The relative bandwidth of the input signal is set to 30 kHz (1/8 of output sampling frequency).  The settings for N, R and M yield a passband attenuation of 0.9 dB and an aliasing attenuation of 68.5 dB. The fixed-point implementation uses two's complement math with rollover.  The largest register is required at the input of the first integrator stage, with a width of 35 bits.  The input and output signals are set to bitwidths of 16; their decimal widths are set to 0.

Note:

It is important to understand that a CIC decimation filter contains integrator sections with unity feedback, which are unstable if floating-point math is used.  The CIC filter implementation is possible only if fixed-point two's complement math with rollover is used.  Therefore, the output of the floating point implementation will diverge and is not useful for real designs; it is provided here only for information purposes.

Reference:

[1] E.B.Hogenauer, "Digital Filters for Decimation and Interpolation," IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. ASSP-29, No.2, April 1981, pg.155-162.

System Diagram - CIC Decimation Filter

Graph - Spectrum