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Design Notes

Circuit Envelope Co-Simulation

This project is setup to show how to do Circuit Envelope co-simulation from VSS including passing internal Circuit Schematic nodes to the System Diagram and performing a basic time domain verification of the DUT.  The amplifier used can be seen in the "High_Power_Amp" Circuit Schematic.  Circuit Schematic test benches are used to verify the frequency domain and time domain behavior of the "High_Power_Amp" and a Circuit Schematic subcircuit is setup for the Circuit Envelope co-simulation.  Additionally, there are System Diagram test benches for verifying the time domain behavior of the "High_Power_Amp" and driving "High_Power_Amp" with a modulated signal to compare the result with a behavioral model of the same amplifier.  Many of the test benches and other Circuit Schematics / System Diagrams have text notes on them to explain some of the details or interesting points about the design.  Lastly, this project uses Simulation Filters since the modulated signal Circuit Envelope simulation takes a few minutes.

Overview

The Circuit Envelope simulation engine can be used as a circuit simulator in Microwave Office or to co-simulate Circuit Schematic with VSS System Diagrams.  This example project focuses on the latter approach but does use the Circuit Envelope simulator in Microwave Office for verification of the DUT in the time domain.  Circuit Envelope co-simulation is performed by using the NL_S_ENV block in a System Diagram.  Like the NL_S block, the NL_S_ENV block points to a Circuit Schematic. 

Because Circuit Envelope is much more flexible than the behavioral model behind the NL_S block there is some additional NL_S_ENV configuration that the NL_S block doesn't have.  More specifically the RF input ports, DC input ports, output ports, and center frequency for each port need to be defined.  See the "Modulated_Signal_System_Test_Bench" System Diagram for more details on the setup.  Note that time step is configured using variables in the System Diagram.

The Circuit Schematics, System Diagrams, Graphs, and Simulation Filter relevant to verifying that the "High_Power_Amp" works well in the time domain can all be found in the "1) Verification" User Folder.  Open all of the items in the folder, enable the "Verification" Simulation Filter, and run the circuit and system simulators to see the verification results.  Similarly, the Circuit Schematics, System Diagrams, Graphs, and Simulation Filter for using a modulated signal with the "High_Power_Amp” can all be found in the "2) Modulated Signal" User Folder.  Open all of the items in the folder, disable the "Verification" Simulation Filter, and run the system simulator to compare the performance of "High_Power_Amp" with Circuit Envelope to a behavioral model of "High_Power_Amp" when driven with a moderately wide band signal

AM_to_AM_Test_Bench Circuit Schematic

This test bench is used to simulate the frequency domain AM/AM and AM/PM behavior of "High_Power_Amp" using Harmonic Balance and to simulate the time domain AM/AM behavior of "High_Power_Amp" using Circuit Envelope.  It is also the subcircuit for the NL_S block (AM/AM and AM/PM based behavioral model) and NL_S_ENV block (Circuit Envelope co-simulation) of "High_Power_Amp" in the "AM_to_AM_System_Test_Bench" System Diagram.

AM_to_AM_Test_Bench_TD Circuit Schematic

This test bench is the same as the "NL_S_Test_Bench" but has a special APLAC setting that causes Harmonic Balance to simulate using a time domain netlist for the "High_Power_Amp".  This is an important intermediate step in verifying that device works properly in the time domain since that's needed for Circuit Envelope simulation.  If there are issues such as negative inductors, s-parameters that extract poorly to the time domain, un-supported elements, etc. they will all be identified by this schematic.  The special option is FreeText=NETLIST_TD in the APLAC secondary options list.

NL_S_ENV_Subcircuit Circuit Schematic

This is the subcircuit which is referenced by the NL_S_ENV block in the "Modulated_Signal_System_Test_Bench" System Diagrams.  Note that the internal voltage / current probe pins are passed up to the System Diagram using PORT_NAME elements.

AM_to_AM_System_Test_Bench System Diagram

This test bench is used to simulate the AM/AM and AM/PM curves of "High_Power_Amp".  Because the "High_Power_Amp" is simulated with the NL_S_ENV block this test bench is using Circuit Envelope co-simulation.  The goal is to have an identical AM/AM and AM/PM response with the "AM_to_AM_Test_Bench" Circuit Schematic results which indicates that the model is functioning properly in a time domain simulation and ready for analysis with modulated signals.  This System Diagram also shows the how to setup the NL_S_ENV block to look at higher order harmonics in a system diagram.  Because each pin in a System Diagram can only have a single frequency one pin is needed for each desired harmonic.  In the "AM_to_AM_Test_Bench" the RF_Out_2 (Port 3) and RF_Out_3 (Port 4) ports are connected to voltage probes on the "High_Power_Amp" output (i.e. they replicate the amplifier output).  On the NL_S_ENV instance in this System Diagram OUTPORTS 3 and 4 are set to output "2f1" and "3f1" frequencies which is the equivalent of the 2nd and 3rd harmonic.  Note that the frequencies are defined symbolically to make it easy to configure the block and not worry about changing simulation frequencies.

Modulated_Signal_System_Test_Bench

This test bench compares the results of "High_Power_Amp" modeled at the system level with NL_S (AM/AM and AM/PM based behavioral model) and NL_S_ENV (Circuit Envelope co-simulation).  The modulated signal is multi-carrier and has ~10% bandwidth ratio so some deviation between the approximation of a single tone AM/AM and AM/PM and the Circuit Envelope co-simulation is expected.  Much like the "AM_to_AM_System_Test_Bench" System Diagram the NL_S_ENV instance in this System Diagram has several "High_Power_Amp" voltages and currents passed as well as a DC supply pin (which is necessary for envelope tracking simulation).  In this case the extra "probe" pins contain DC current and voltage (equivalent of Icomp or Vcomp measurement at harmonic 0) at the transistor's collector pin.  The supply pin (pin 5) is driven with a SRC_R which is the VSS equivalent of a DCVS in MWO.  Of course this pin could be connected to anything, including a time varying waveform for more advanced simulations.

Verification AM to AM Fundamental Graph

This graph shows the fundamental AM/AM response from the "AM_to_AM_Test_Bench" Circuit Schematic using both Harmonic Balance and Circuit Envelope, the "AM_to_AM_Test_Bench_TD" Circuit Schematic using Harmonic Balance with a time domain netlist, and the "AM_to_AM_System_Test_Bench" System Diagram. 

Verification AM to PM Fundamental Graph

This graph shows the fundamental AM/PM response from the "AM_to_AM_Test_Bench" Circuit Schematic using both Harmonic Balance and Circuit Envelope, the "AM_to_AM_Test_Bench_TD" Circuit Schematic using Harmonic Balance with a time domain netlist, and the "AM_to_AM_System_Test_Bench" System Diagram. 

Verification AM to AM 2nd Harmonic Graph

This graph shows the 2nd harmonic output response from the "AM_to_AM_Test_Bench" Circuit Schematic using Harmonic Balance, the "AM_to_AM_Test_Bench_TD" Circuit Schematic using Harmonic Balance with a time domain netlist, and the "AM_to_AM_System_Test_Bench" System Diagram.  This graph was added to illustrate how probing for circuit level higher order harmonics from a System Diagram works.

Verification AM to AM 3rd Harmonic Graph

This graph shows the 3rd harmonic output response from the "AM_to_AM_Test_Bench" Circuit Schematic using Harmonic Balance, the "AM_to_AM_Test_Bench_TD" Circuit Schematic using Harmonic Balance with a time domain netlist, and the "AM_to_AM_System_Test_Bench" System Diagram.  This graph was added to illustrate how probing for circuit level higher order harmonics from a System Diagram works.

Verification Delta Graph

This graph computes the delta between the AM/AM and AM/PM response between the "AM_to_AM_Test_Bench_TD" Circuit Schematic HB and Circuit Envelope result and the and the  "AM_to_AM_Test_Bench_TD" Circuit Schematic HB and "AM_to_AM_System_Test_Bench" System Diagram result.

Modulated Signal Spectrum Graph

This graph shows the input spectrum to the NL_S and NL_S_ENV blocks in the "Modulated_Signal_System_Test_Bench" System Diagram.  It also shoes the output spectrums from the NL_S and NL_S_ENV blocks.

Modulated Signal Collector Voltage and Current Graph

This graph shows the voltage and current waveforms on the collector pin of the transistor while the device is driven with a modulated signal.  This setup is to illustrate how to probe internal circuit nodes from a System Diagram.

Modulated Signal PAE Graph

This table shows the "High_Power_Amp" PAE (time averaged) as it's driven by a modulated signal in a System Diagram.  Note that setting up a system level PAE measurement requires that the NL_S or NL_S_ENV block has the DCPOUT parameter set to Yes.

System Diagram - Modulated_Signal_System_Test_Bench

Graph - Modulated Signal Collector Voltage and Current

Graph - Modulated Signal Power Spectrum