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This project forms a basic Direct Digital Synthesizer (DDS) architecture
Equation for DDS architecture:
FOUT = (M (REFCLK)) /2N
FOUT = the output frequency of the DDS
M = the binary tuning word
REFCLK = the internal reference clock frequency (system clock)
N = The length in bits of the phase accumulator
Basically the smaller M, the more output samples per cycle of REFCLK and lower the output freq.
The Phase accumulator is formed by loading the tuning word M into SRC_R ID=A28 and is incremented by the ADD loop.
A binary phase offset is added by SRC_R ID=32. The MOD element performs Modulo 255 math on the phase since this is an 8 bit counter and outputs the remainder.
The Lookup table contains a sine wave with 256 entries. The output from the MOD element acts as the index to the lookup and is rounded up.
In this example:
f_Clk = 250MHz
f_out = 10MHz
n is 8 bits so M is 10.24
Ignoring the phase offset, the first loop in the table would be index 11, the second would be 21, the third 31 and so on.
It is the rounding errors of the index value that form the spur variation as M is varied to produce a new output frequency.
A basic tutorial on DDS can be found at: