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Design Notes

Digitally Controlled Capacitance Using Vector Instances

This example is to show different ways that vector instances can be created in a schematic.   The different techniques will be demonstrated with a circuit that uses a digital signal to enable or disable capacitance seen by the rest of the circuit.  

Overview

Many times designers want to tune their circuits with digitally controlled capacitance.  This schematic has such a block, in the schematic called “Tune_Cap”, in this case it is a differential circuit.  When the control signal is high, the circuit will see the two capacitors, when low, this circuit will be an open circuit.  

In this example, there are three bits that will control the amount of capacitance added to the circuit.   This is done by having each control bit increasing the number of the “Tune_Cap” subcircuits turned on.  Since there are three bits, we need 7 “Tune_Cap” blocks, bit 1 controls one block, bit 2 controls two blocks, and bit 3 tcontrols four blocks.  

This project will show 4 different approaches to this problem.  In each case, we are sweeping an integer for the digital state, in this case 0 to 7.  The subcircuit “DIGSRC_BUS” takes in this integer and creates a Bus output with the correct voltages for each bit line. 

This example will then use vector instances which are a way to have many instances of one schematic element used in simulation and layout.   You can change any elements Vector instance by opening up the elements properties, clicking on the Vector tab and then using the syntax [0:N],  where N is the N-1 number of instances.  For 4 instances, you would use [0:3].  You can also edit the ID of each element to use this syntax.  

Digital Source Response

The “DIGSRC” subcircuit takes in an integer number and decodes the proper voltage for each bit of the bus coming out of this block.  To see this in more detail, open up the “A_Tune_Cap_No_Vector” schematic and simulate the project.  Then zoom into the output of the “DIGSRC” subcircuit.   You will see the output voltages annotated for that bus.  Open the tuner (Simulate > Tune from the menus).  Then slide the tuner to change the digital state and see what happens to the output voltages.  

Results and Layout

For each of the methods described below, you can see the effective capacitance versus frequency and digital control stage on the graphs that start with the same letter as the schematic for that method.  The graph “E Cap at 2 GHz”, is showing the results of all the methods, with the control state on the x-axis and at a single frequency of 2 GHz.   Also, you can view the layout for each method to see they are identical.  

Method One

The most obvious method is to have 7 instances on the schematic all wired together.  This approach is done in the schematic “A_Tune_Cap_No_Vector”.  There are 7 subcircuits of the “Tune_Cap” with all of their outputs wired together.  The control lines are individually connected to each block.   This method works but you can see a schematic will get very messy in a hurry with any complexity. 

Method Two

The next method is to have one “Tune_Cap” subcircuit for each control bit.  This is done in the schematic “B_Tune_Cap_Vector_Instance”.  In this case there are 3 subcircuits and those for bit 2 and bit 3 are using a vector instance.   The subcircuit connected to bit 2 has the S3[0:1] vector instance and the subcircuit connected to bit3 has S4[0:3] vector instance.   This method looks better on the schematic. 

Method Three

The next method is to have one “Tune_Cap” subcircuit total and then control how the control signals are hooked up.   This is done in the schematic “C_Tune_Cap_One_Vector_Instance” .  Note that the “Tune_Cap” subcircuit has 7 instances from the ID parameter of S1[0:6].  Then the named connector at the Tune node is a comma separated list of the control signals, tune[0],tune[1],tune[1],tune[2],tune[2],tune[2],tune[2].   Notice how much cleaner this schematic looks than the first method. 

Method Four

The final method is a slight various of method three.  This is done in the schematic “D_Tune_Cap_One_Vector_Instance”.  The only difference is how the bits are connected to the Tune  node.  Instead of listing all 7 control lines, you can list the number of each control line, tune[0],2*tune[1],4*tune[2]. 

Schematic - D_Tune_Cap_One_Vector_Instance

Schematic - B_Tune_Cap_Vector_Instance

Schematic - A_Tune_Cap_No_Vector

Schematic Layout - A_Tune_Cap_No_Vector

Graph - E Cap at 2 GHz