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Design Notes

MULTI-LAYER PCB DESIGN EXAMPLE

This example is courtesy of Ericsson Microelectronics AB, Kista, Sweden

The aim of this project is to show a complex six layer LPF file in operation on a real design incorporating 3D views, to optimize a circular test board design.  The only original information is a GDSII file from the finished layer stack and the ideal component schematic with no layout information.  These two sources of information need to be tied together in the AWR Design Environment (AWRDE).

Overview

This project uses a six layer LPF file to simulate the input match from SMA connector modeling as multiple EM via holes, through SMT components on a six layer PCB up to a multi-pin SMT package.  The complete board is a test fixture for a high frequency, multi pin FPGA.  The importance here is to ensure that the injected power does indeed get to the FPGA chip.

Starting from only an original GDSII artwork layout and an ideal component schematic, the "Ideal_Schematic" design can be generated.  This is further enhanced with real microstrip lines in the "Ideal_Schematic_with_TX_Lines", making heavy use of the MCTRACE/MTRACE2 elements to route the design in the layout view whilst keeping an accurately represented schematic design.  The original GDSII layers were copied into the schematic layout in order that the final schematic elements EXACTLY copied those of the original design.  The tune tool can be used here to adjust line lengths and widths while watching the modified layout window.

The board outline is copied from the original GDSII file into the layout window so that the lines are correctly located with respect to the vias in the board and the overall board outline.

An electrical model for the balun component was unavailable.  A proposed internal design is suggested based on the data sheet information.  Component values are optimized  for insertion loss and match results to obtain an identical response to that given in the data sheet.  The optimizer goals are still apparent on the balun graphs.

The SMT components are placed on the underside of the board with careful 3D mapping settings.  These can be found under the "Layout" tab, double click on Layer Setup, select  3D properties.

The 3.5mm SMA connector was modeled as an EM structure using stacked multiple vias through each level of board.

Once the design had been produced, the final task is to optimize the layout and component value for best input match at 900MHz ± 100 MHz.

An optimized design was achieved.

Simulation Plots

“Port Match at Output” shows just how critical the layout is to the simulation results.  Once lines have been added to the schematic, “Port Match with TX Lines” indicates the optimized input match. 

Ideal Schematic

This is the starting point where the ideal schematic can be entered into AWRDE, as archived on site at Ericsson.  This design contains NO layout information,

Ideal Schematic with TX Lines

Beginning with the “Ideal_Schematic”, microstrip line models are added with arbitrary parameters.  These lines are adjusted in the layout to overlay those from the original GDSII artwork.  As the adjustments are made, the dynamic link between layout and schematic ensures that the schematic element properties follow those of the layout items.  MCTRACE elements can be used to add bends and arbitrary angles to the layout microstrip lines.

SMA_Connector & EM Vias

To correctly model the SMA connector pin penetrating the six layer PCB stack, via holes were used for each layer transition.  These can then be stacked together in the linear schematic to produce an accurate model for the input connection.  This would be even more important if the various layer materials were not identical.

Balun LDB20 Impedance and Insertion Loss

With no electrical model for the internals of the SMT balun device, a schematic was proposed with unknown stray components.  The results can be plotted, and these component values optimized until identical results are obtained as given in the datasheet.  At this stage, even if the proposed schematic is not absolutely correct, the S-Parameter performance of the SMT device over the narrow frequency band is sufficient to complete the final design work.

Modeling and Simulation

Linear only circuit elements are combined with 2½D electromagnetic models for the SMA connector pin to produce an accurate set of results for this design.  The importance here is to ensure that the injected power does indeed get to the FGPA chip.

Optimization

Optimization is used in two instances within this project.  The first is on the LDB20 Balun device, in order to optimize the proposed model for the balun device to be identical to the results provided in the device datasheet.

Once the design is finished, the optimizer is used on the SMT component values in order to produce an optimized match at 900MHz ± 100MHz.  The next stage would be to use a fixed list of real part values from which to choose  such that the optimizer produces a realizable component value list.

Schematic - Balun_LDB20

Schematic - Ideal_Schematic_with_TX_Lines

Schematic Layout - Ideal_Schematic_with_TX_Lines

Graph - Attenuator Insertion Loss