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Design Notes
FET Multiplier
This project demonstrates how to set up the AWR Design Environment for the nonlinear simulation of a FET frequency doubler. It also demonstrates some of advanced AWR capability such as using the tuner to control the display of the simulated data. In this mode, the tuner is also employed in the same fashion as when tuning circuits, only it's tuning through already simulated data. The tuner is a very powerful tool allowing designers to control the results of complex simulations.
Overview
This multiplier uses a single transistor whose bias is fixed at just below the specified pinch off voltage of the channel; this ensures that the device produces an output waveform that has a fairly strong second harmonic content. Other arrangements are possible, such as combining two transistors in anti-phase, but for the purposes of this example project one transistor is used. With this simulation two parameters are being used to explore the circuit behavior, namely frequency and drive power. The drive frequency is defined using the individual options for each schematic. All circuits schematics (and EM Structures) have own their own frequency ranges. Right click on "FET Frequency Multiplier" in the project browser and select Options in the menu. On the Frequencies tab you will see the frequency list used to define the simulation frequency set. To define the drive level, an equation has been placed in the schematic that sets up the range of power values. A complimentary equation defines a variable "Power" that is indexed to the list of potential powers used in the simulation. In this example, the list of power levels is defined by the statement "PowerStates = stepped(9,13,0.5)".
DC and Dynamic IV
The instantaneous voltage at the device terminals is plotted along with the DC static IV curves. These serve to give some insight into the device behavior under these extreme drive conditions. As a check on the bias conditions, edit the schematic "FET Frequency Multiplier by substituting the PWR parameter for the input port with "-20". Re-simulate and the quiescent operating point will be seen. The schematic "FET DC IV Tests" is used for the simulation of the DC IV curves of the transistor.
Output Spectrum
To assist the designer in seeing the actual drive frequency and the frequency of the associated second harmonic, markers have been added to the traces of the fundamental and second harmonics. The markers will update while the tuner (Simulate > Tune) is being used giving instant feedback as to the drive frequency. To see the marker snap to the trace, after each movement of the tuner bar release the mouse button before moving the tuner bar to the next position.
Waveforms
The time domain plot of the multiplication process can readily be seen when comparing the drive waveform and the load waveform. Use the tuner to vary either the drive level or the frequency.
Tuning
The dynamic IV measurement (IVDLL)shows post simulation tuning feature. This feature allows the designer to select the simulated traces using the tuner. In this project, the IVDLL is calculated for all the frequencies associated with the project, the tuner (Simulate > Tune) allows the display of a single trace at each of the frequency.