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LTCC Amplifier Module
This project is a real LNA implemented on LTCC. It was designed and built by one of our customers. It illustrates some of the advantages of LTCC over traditional PCB technologies, such as reduction in size and very good broadband performance.
This example demonstrates the use of the *.lpf file in order to produce multi-layer designs on substrates such as LTCC. (NOTE: The LPF is included as a Data File in this project. While this is not the correct way to use an LPF, it makes it very easy to examine the LPF while remaining in the AWR environment.) We make use of the layer mapping to translate schematic symbols to the correct layer. Layer mapping is accessed through Options->Drawing Layers and then the Layer Mapping tab.
Hierarchy is used to design each section separately. All of the subcircuits are then combined in the top level "LTCC module" schematic.
The 3D layout view is invaluable to visualize EXACLTY what would be produced on each individual mask layer.
To export individual layers, select Options->Drawing Layers and click the Export Mapping tab. Generate a new Export Mapping (like layer1). Choose the data format (GDSII, DXF, Gerber or PADS) and choose the correct layers to output.
The mask data is generated by selecting the appropriate schematic (top level would be "LTCC Module"), right click and choosing the export layout option. Pull down the Save as type menu, and select the appropriate file mapping.
For GDSII export, "hierarchical" keeps the hierarchy of cell designs within the layout, and "flat" reduces the entire layout to a single entity, eliminating any hierarchy that was used to create the design.
This project is courtesy of BAE Systems.
EM Simulation With AXIEM
The layout for this example could have significant impact on the performance. This circuit is an excellent candidate for EM simulation using AXIEM with the extraction flow. Since this is a fairly complex design, this guide will describe several approaches taken to see how the design changes with EM simulation in stages.
The first area of investigation is the vias on either side of the stripline filter. We can see how the response changes of the circuit by just EM simulating that section of the design. Note the Via_Transition graph that is just looking at the response of the via. In the Via_transition schematic, enable the EXTRACT block. Notice the Hierarchy setting is set to On. This means that when the entire circuit simulates, this via will be simulated and the EM results will be used to model this via where ever used. Notice the response on the LTCC Module graph, it has changed slightly, most noticeably at the high end of the filter. Disable this extraction block to see the original response and enable again to see the EM response.
The next area to investigate is the LNA. Enable the EXTRACT block in the Amp_Extract_Testbench and simulate. This will simulate all of the interconnect for the LNA using AXIEM. Since the amplifier only sees the top ground, the STACKUP for this simulation is simplified to only be a single dielectric layer. Look at the Low Noise Amp Match and Low Noise Amplifier graphs to see the amplifier response with the EM simulation results. Again, you can disable the EXTRACT to see the response without extraction to compare. Notice at 10 GHz, the gain of the amplifier drops significantly.
The next are to investigate is the filter EM simulated with the rest of the circuit. First, the EXTRACT block in the Via_transition schematic needs to be disabled so the via can be included in the complete filter simulation. Second, enable the EXTRACT block in the Filter_Extract_Testbench and simulate. See the LTCC Module With Extracted Filter graph for the response of the entire circuit with the filter done with AXIEM.
Finally, if you want to simulate the entire circuit, enable the EXTRACT block in the All_Extract_Testbench and simulate. See the LTCC Module graph for the response of the entire circuit metal simulated with AXIEM.
The EM documents that are extracted in this project are set up to use AXIEM autoports. To see how the ports are configured for an EM structure that uses autoports right-click on the EM structure and preview the geometry. Look at the preview of the EM_Extract_all EM structure and notice that the ports where the capacitors are placed on the lower bias line are set up to be a mutual grouping pair. This ensures that when de-embedding takes place of these ports, it accounts for the port next to it.