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Design Notes

1 Watt X-band HPA MMIC

This example shows a 1W X-band HPA MMIC design utilizing the example AWR MESFET PDK with APLAC HB, simulation switch lists, and linear power estimation using the Cripps method implemented with Output equations.



This project has a full HPA design including simulations and layout of a 1W HPA MMIC using the example MESFET PDK.  The project illustrates the use of kit PCELLs elements, APLAC simulations, and optimization using Output Equations for output power and power margin estimated with the Cripps Linear Power estimation method.  This project also illustrates the usefulness of Connectivity Checker to verify the DC connections across the chip: a preliminary step to reduce errors before performing a formal LVS.

Cripps, S.C., “A Theory for the Prediction of GaAs Load-Pull Power Contours”, IEEE-MTT-S Int’l. Microwave Symposium Digest, 1983, pp 221-223.

Project Schematics


Circuit schematic contains the entire amplifier with bondwires connecting to the module level.  HPA_MMIC is the MMIC schematic by itself.


Schematic containing the Output Matching Network (OMN) as a two port network which is required for the Cripps output equations which operates using the ZIN() measurement.  The inductance in the schematic is used to account for the manifolds which are included in the FET simulations when the loadpoints were extracted from simulated load pull of the FETs.  This schematic is used to design the OMN to achieve the desired output power.


Schematic contains the InterStage Matching Network (ISMN), Output FETs, and OMN all as a two port network.  This schematic is used to design the ISMN in order to get the adequate power drive margin between stages.

LoadTarget_OMN LoadTarget_ISMN

Schematics used to determine where the FET periphery load targets are on the smith chart for comparison to the matching networks.



Schematic with a simple parallel RC to RF ground to show a given periphery's load point on the smith chart.

Output Equations and Simulation

The Cripps Linear Power Estimation method is used in this project to calculate the output power and power margins between the two stages.  The equations are implemented in the Output Equations using the impedance measured from the Cripps_OMN and Cripps_ISMN networks which are two port equivalents of the actual networks themselves.  The output equations use the values from the Global page of Output Power per mm of FET periphery (Pout_mm), equivalent parallel resistance and capacitance of the load target (Rpmm and Cp_mm).  These values can be obtained from the load pull of the target FET either simulated or measured.

Cripps, S.C., “A Theory for the Prediction of GaAs Load-Pull Power Contours”, IEEE-MTT-S Int’l. Microwave Symposium Digest, 1983, pp 221-223.

The equations on the output equations are totally linear in nature and can properly estimate output power based on the load target supplied to the calculations assuming proper power compression level of a FET.

To see nonlinear simulation results enable the measurements in the 10_GHz_Power_Sweep graph.

User Folders

Linear SParms folder contains the top level schematic and linear simulation graphs for the 1W HPA.  The simulations use the linear S-Parameters for the FET performance instead of the non-linear FET

NLinear Sims folder contains the non-linear schematic and performance graphs using the APLAC simulator for simulation

Cripps Power folder contains the Cripps graphs for output power and power margin for the design

Connectivity Checker and Highlight

The Connectivity Checker does a preliminary verification of connectivity in the layout compared to the schematic.  It does not replace formal LVS, but "catches" most errors before formal LVS is used.  Open the HPA_MMIC schematic layout, and use Verify > Run Connectivity Checker to see that there are no errors.  Now intentionally modify the layout (anywhere in the hierarchy) to change the layout connectivity, and run Connectivity Checke r again to see the errors.  For example, move the via at the center of the layout, which is not in a subcircuit.

The Highlight Connectivity feature is nice for tracing DC connections through the whole layout.  Open the HPA_MMIC schematic layout, and use Verify > Highlight Connectivity All to look at all of the DC connections in either the 2D or 3D layout view, or use Verify > Highlight Connectivity Probe to enable and disable highlight of DC nets one at a time.  The 3D view changes to a wire frame, which makes it easier to follow individual highlighted DC connections.