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Multi-Layer PCB Configuration
This example illustrates the method used to configure multi-layer PCB design in MWO. A 3-layer PCB is shown, with traces on all 3 layers and vias between the layers.
Note that this example shows only the setup techniques for a multi-layer PCB. There is no analysis associated with this project. Throughout this example, it will likely help if you have the completed example and its LPF open in separate MWO and Notepad windows as you work through the sequence in a second MWO project. Your licensing should permit two simultaneous instances of MWO on your desktop.
This example will explain many of the details of setting up an lpf. A utility is available to help automate this process, available from Tools > Create New Process...
The .LPF File
Most of the required setup can be performed in the Layer Setup dialog (Options>Drawing Layers...). Two portions of the setup, however, require manual editing of the Layer Process File, or LPF for short. These two actions are the definitions for line types and vias. The LPF can be edited with any text editor. (If you use Notepad and you save a new file, be sure to enclose the file name in quotes to avoid inadvertently appending ".txt" to the file name. A file named Sample.LPF.TXT will not work!)
NOTE: The completed LPF for this example, PCB.LPF, is included as a Data File in this project. While this is not the correct way to use an LPF, it allows you to look at the completed LPF while reading the remainder of these "Design Notes". This should be very valuable as you learn about LPF's and how they work.
Understanding the Layer Setup
In order to understand the layer configuration process in the most straightforward manner, it is recommended that you use the following procedure:
• Create a new project. On the menu, select Project>Process Library>Import LPF..., load "Blank.LPF" from the main AWR installation directory, and replace your current LPF with it. This LPF represents the minimum layer configuration for AWR. Even if these layers are manually deleted, they will be automatically recreated (without any layout entities that may have been on them) when the LPF is regenerated. We will use this LPF as the basis for the remainder of this example.
• On the menu, select, Project>Process Library>Export LPF... and write the LPF to your desired location. Open this file in Notepad. We will concern ourselves here only with the portion of the file that is above the line that says "Drawing Layer Setup Defined Below".
• Note that there are several header/footer combinations that define sections that are largely empty. We will make manual additions below.
• Refer to the original PCB.LPF for the exact changes that are made to the default Line Type, Via and STRUCTure definitions. Beyond the default configuration, Line Types, a Via definition (only ONE via definition allowed in a LPF), and STRUCT definitions have been added. All other changes to the LPF can be handled from within the AWR Design Environment.
• The Line Types represent a definition for each metal layer (Copper_1, ...) and a special Line Type that draws all three substrate layers in a single operation (PCB_1, ...).
• A Via definition is present. The via definition uses dummy layers (Via_Top, Via_Hole, and Via_Bottom). These layers are mapped to different drawing layers below, which allows vias to be placed on any layer and still have the proper layer assignments. This is covered in more detail in the Mapping section below. Also, note the "Offset" and "Flags" settings in the via definition. These parameters create, in this case, the annular rings and define the via as round with its reference plane at the center of the hole. The documentation addresses LPF details in: MWO/AO Layout Guide > Layout Editing > The Layout Process File (LPF). (NOTE: Via offsets are specified in meters!!)
• Once the Line Types, Via definition, and STRUCT definitions have been added to the LPF, it can be saved and closed.
• In MWO, import the LPF and open the Drawing Layer Options dialog box (Options > Drawing Layers...). The default selection should be Drawing Layer 2D on the left side. (For comparison in the following steps, open the same dialog box in this project, which uses the PCB.LPF file.)
• The additional drawing layers can be added and re-ordered here: Copper_1, Copper_2, Copper_3, Via_12, Via_23, Package, Leads, PCB_1, PCB_2, PCB_3. It will become apparent how these layers function below.
• Next, select Drawing Layer 3D on the left side of the dialog. The entries in the "Z Position" and "Thickness" columns specify how things appear in the 3D view only. (NOTE: 3D values are entered in nanometers!! Please refer to the corresponding dialog box in this project, for a set of example values.)
• Next, select Model Layer Mappings, which will have one mapping called ModelMap1. Here, we need a total of three mappings. Rename the existing mapping to "Layer 1" (right-click and select Rename...). Then, add new mappings called "Layer 2" and "Layer 3". (Right-click Model Layer Mappings and select New Model Layer Mapping.) In each mapping, drawing layers are mapped to their twin model layers, EXCEPT the via layers (The GDS model layers, with names like 10_0, ... are beyond the scope of this example). The via layers are mapped differently for each layer mapping, with assignments made to various metal and via drawing layers. Please refer to corresponding dialog box in this project for each mapping of the three Via layers (Via_Top, Via_Hole, and Via_Bottom).
• Where these entities appear in a layout window, 2D or 3D, is handled by mapping the model layers to drawing layers. In this way, we can assign the dummy via layers to different drawing layers in each separate mapping definition. So, for the "Layer 1" mapping, dummy model layer Via_Top maps to drawing layer Copper_1, dummy model layer Via_Hole maps to drawing layer Via_12, and dummy model layer Via_Bottom maps to drawing layer Copper_2. Look at the mapping assignments for the other two layer mappings and you should begin to get an idea of how this program capability works.
• This completes the layer setup procedure. To wrap up, we will look at how the various elements are configured in schematic and layout.
• Once a schematic is drawn and a default layout is created, we must assign various line types and layer mappings to the layout elements.
• In the layout window, select a component, right-click, and select Shape Properties. Note the Line Type and Layer Mapping settings for each element.
Discussion of Options for Via Configuration
As shown in this example, the layer mappings can effectively move a single via definition around the layer stack. This works well if the only via transitions are to/from adjacent layers. If the via is to traverse more than adjacent layer connectivity, the method described above will produce an annular ring (or "catch pad") on each intermediate layer, which is usually not desired. To solve this problem, we can define vias in another manner.
Look at the three STRUCT definitions in the LPF. There is one for the via from layer 1 to 2, one for layer 2 to 3, and a third one for layer 1 to 3. This third STRUCT includes an extra layer for the via and only draws the annular rings on the top and bottom layers, which is usually desired.
To set the STRUCT assignment for individual vias, we must work from the schematic, not the layout. Double-click the schematic via symbol and make sure the "Show Secondary" button is clicked. The "SNAME" parameter is where we enter a string pointing to the STRUCT name.
The schematic called "STRUCT Vias" is exactly the same as the "PCB Lines" schematic, but the vias are manipulated with STRUCTs, not layer mappings. Note that the layer assignments in the STRUCTs are explicit - no dummy mapping layers are involved.
Is one via technique better than the other? No, it depends on what you are trying to do. Just keep in mind that you can only have one VIA_DEFINE_BEGIN/END block in your LPF. Using this method, all vias will look the same, even though they are drawn on different drawing layers. Using the STRUCT method, we are able to create vias with completely different physical configurations, as we see in the transition from layer 1 to layer 3. Carefully examine both schematics and their layouts to be sure you understand the various concepts presented in this example.