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Where To Find This Example

Select Help > Open Examples... from the menus and type either the example name listed above or one of the keywords below.

Or in Version 14 or higher you can open the project directly from this page using this button. Make sure to select the Enable Guided Help before clicking this button.

Design Notes

This project must be saved in a folder with write permission to simulate with extraction.

Before simulating, select File > Save Project As... and save in a different folder.

Op-Amp Project

This project demonstrates the ability of Analog Office to perform full characterization of a high frequency operational amplifier in the Generic BiCMOS PDK. The project can be described as an automated spread-datasheet generator where many of the important amplifier figures-of-merit are determined over variations in temperature, power supply, process corners and load capacitor. The project highlights the power of the measurement driven design environment where design changes can be quickly re-characterized with the click of one icon.


The operational amplifier is made up of a number of stages identified in the circuit schematic:

1. Input stage - a classical differential transistor pair gain circuit driving matched resistive loads and biased by a current source

2. Voltage level shifter - differential emitter-followers that drive diode- and resistor-level shifters into a differential-to-single-ended converter

3. Differential-to-single-ended converter - as the name implies, this circuitry converts the differential voltage through the level shifter to a single-ended signal

4. Common emitter gain stage with PMOS current source load. This stage is driven by the output of the converter and generates most of the gain of the amplifier

5. Emitter follower output stage with NPN current source bias - this stage buffers the gain stage high impedance node from the output load

6. Bias network - this circuitry establishes all the current sources in the amplifier.

The project is configured into four Test Benches, one each to measure DC, AC, SRR, and transient performance specifications. The amplifier is also rated to operate over positive power supply voltage corners of 3.7v to 4.3v and a load capacitor range of 0-1pf. Accordingly, parameter sweep blocks are included in all the Test Benches for the power supply and load capacitor. Temperature and process corner sweeps are also defined in the Test Benches. The measurements included in this project are:


The DC operating conditions including power, output voltage and input offset voltage are shown in Graphs DC output voltage and DC Power.

The AC performance factors including open and closed-loop small signal gain and phase as well as the positive/negative power supply ratios are shown in Graphs titled Open and Closed Loop Gain and Phase and Supply Rejection Ratios.

Transient time-domain unit-step overshoot as well as positive and negative large-signal pulse overdrive characteristics are shown in Graphs titled LS Step Resp and SS Step Resp.

Also shown in the project is the detailed layout of the operational amplifier in 2 and 3D as well as the interconnect network used for RLCK extraction.


The Goal of this demo is to impress upon the viewer the power of the AWR measurement-driven environment to perform automated and comprehensive characterization of the amplifier in a number of Test Bench configurations. Designers who use other EDA systems are reluctant make an improvement to their design late in the cycle because of the arduous re-work necessary to re-validate the design after a change. The reuse and efficiency of the AWR environment makes it easy to make design changes and quickly re-characterize the design. Proceed as follows:

� After bringing up the project, go through the circuit and different Test Benches/graphs to show the variety of configurations and measurements that are included. Bring up the Output Equations form to show how some measurements can be built out of mathematical expressions of the simulation results. You can also show the layout in 2 and 3D as well as the extracted net view.

� Then click the Analyze icon to start the characterization process. This process will take around 2 minutes.

� At this point, you may want to freeze the graphs and then go to the circuit schematic and change a design parameter (any capacitor, resistor or transistor parameter will do). Make the change minor so as not to cause the circuit to malfunction. With one-click of the Analyze icon, all the measurements are updated.

� Now go to one of the Test Benches and change a parameter and re-Analyze. This will demonstrate how (like an Excel spreadsheet) only those measurements dependent on the changed parameter are re-evaluated. The range of the supply voltage in Sweep Block "VccDC" in the DC Test Bench is a good one to choose. Change it from "3.7, 4.3" to "3.5, 4.0" and notice only the DC simulations are run and only the DC measurements are updated.


Note that Extract Blocks in the test benches are disabled. Extract can be enabled by right clicking the Extract block and choosing Toggle Enable. In the layout view, choose only the iNets to be extracted. If other elements such as capacitors and transistors are selected, the extraction engine will give errors. Once the desired iNets are selected, right click on any selected iNet and choose Element Properties and go to Model Options in the dialog window. Check the Enable option and Group name: EM_Extract. During the next simulation run, the iNets will be extracted for the selected parasitics. RLCK or a subset can be selected by double clicking on the EXTRACT block and selecting the NET-AN Options tab. Here, all the RLCK and subsets options are available. Simulating every iNet in the design will actually cause convergence problems in this particular design. So, selecting only the critical iNets is required.

Schematic - SRRTestBnch

Schematic Layout - Generic_Opamp

Graph - Open and Closed Loop Gain and Phase

Graph - Supply Rejection Ratios