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AWR Version 14
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AWR Version 13
This example was renamed since the previous version. Please see Previous Example Page for the version 13 page.
CMOS OpAmp project
This project shows a CMOS Operational Amplifier designed with AWR Generic Silicon Process Design Kit. This OpAmp has cascoded first stage to get higher gain without having to add another common-source stage. The first stage is followed by level shifter and output stage. OpAmp also has a simple bias circuit located in the left part of the schematic.
This project also shows the measurement setups to simulate basic OpAmp characteristics; transfer function (Bode plot), CMMR, PSRR, DC function and pulse response.
This project is divided into multiple schematics. Each schematic represents as test bench to measure different OpAmp characteristic. The name of the schematic tells what OpAmp characteristic it is used to simulate. All the measurements are done with HSpice DC, AC and transient solvers.
Open the schematics and corresponding graph to see the simulation setups and curves. See the correspondence below:
“AC test” -> “Bode Plot”
“CMRR test” -> “CMRR”
“PSRR test” -> “PSRR”
“DC test” -> “DC transfer”
“Transient test1” -> “UnityGain Pulse Response”
“Transient test2” -> “Pulse Response”
“Inet current density” test bench is used to annotate current density of each Inet to layout. To see the current densities in the layout open the schematic “Inet current density” and choose View > New Layout View.
To see more advanced OpAmp project with simulations over PVT open the example project “OpAmpNPN”. You can also find more information about Inet current annotations from example project “Current_Density_Annotation”.