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Design Notes

PLL with Phase Noise

This example demonstrates the inclusion of phase noise on the VCO in a PLL.  Please refer to the example PFDCP_DIVIDER_VCO_B in this folder for more design notes.

Note in the system diagram "PLL" the outputs of the VCOs are set to complex. Setting the signal to complex allows you to set the sampling frequency much lower than if the simulation is done in "real" mode.

System Diagram - Phase Noise

System Diagram - PLL

Graph - Charge Pump Current

Graph - Output Spectrum

Graph - V_tune

Graph - Phase Noise Mask