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Design Notes

Efficient APLAC HB for Larger Circuits

This project shows a QPSK receiver implemented at transistor level and simulated with APLAC harmonic balance (HB) simulator. It demonstrates the capacity and speed of APLAC HB, which can take advantage of multi-processor systems and Multi-rate Harmonic Balance for even better performance.

Overview

 

The QPSK receiver is built from four main blocks:

1.   PPF (Poly Phase Filter) that is used to feed Local Oscillator Signal to Mixer with 90 degree phase difference

2.   Down converting differential CMOS Gilbert mixer

3.   Differential to single ended converters for both I and Q channel

4.   Sixth order Bessel low pass filters for both channels to filter the possible LO and RF leakage

Total component count is around 250 components with 130 actives (Bsim3 MOS transistors) and the rest are passives and sources.

Simulation Setup

"QPSK" is one of the top level schematic in this project, and it is used to set up the LO power sweep simulation. The simulation setup for APLAC HB is similar to the one for the traditional AWR HB simulator.

The project frequency of 2.45GHz, set in Options > Project Options… is used for the RF port (PORT1 element, which uses tone number 1).  The PORTFNS element is used for the LO port*.  It includes parameters to specify the tone number (2), the frequency (2.44GHz), and power sweep (-10dBm to 10dBm, in 1dBm steps).  The number of harmonics for each tone is set in Options > Default Circuit Options…

“QPSK_MRHB” is the other top level schematic in this project.   The setup is identical except it is configured to use Multi-rate Harmonic Balance.  This configuration is done by adding MRHB blocks to the schematic, configuring them properly, and then assigning each top level block (sources and subcircuits) to reference each block. 

Simulation Speed

APLAC HB simulator can take advantage of multi-processor or multi-core PCs.  Select Options > Default Circuit Options... > APLAC tab, and in the Harmonic Balance Analysis group, set NTRHEADS to the number of processors to use.

Simulation time for this LO power sweep was less than one minute with APLAC HB and eight times longer with old AWR HB.  The MRHB simulation is approximately 3 times faster.  

Graphs

“LO Power sweep” shows the fundamental output voltage and voltage gain vs. LO power for both traditional and MRHB analysis.  Notice the results are identical.  

“Output Spectrum at I_out Node” shows the output voltage spectrum at the I_Out node. Double click the measurements to see the setup. Use the tuner to adjust the input power level for both measurements. 

“Mixer Output Spectrum” shows the voltage spectrum at output of the Mixer. Double click the measurements to see the setup. Use the tuner to adjust the input power level for both measurements. 

The “Freqs_at_circuit_locations” are some fancy measurements dong with output equations to track the voltage levels of different tones at different levels in the circuit.   The graph comparing traditional HB to MRHB gives good insight into why this works.  The traditional HB shows signal levels for all tones and locations, even though some of them are very small ( < -200 dBV).  The MRHB case shows these values as -800, which is 0 in double precision math, so MRHB did not solve for these frequencies.    

* A note on port selection: Instead of remembering to use a PORTFNS element, for example, you can begin by placing an ordinary PORT element, then right-click on it and select Properties... Go to the Port tab and set Port type to Source, Tone type to Tone 2 and check the Swept power check box. Then go back to Parameters tab and set parameters.

Schematic - QPSK_MRHB

Graph - Freqs_at_circuit_location

Graph - Mixer Output Spectrum

Graph - Output Spectrum at I_out Node

Graph - LO Power Sweep

Graph - Freqs_at_circuit_location_HB_vs_MRHB