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Design Notes


Simulation of 2.5V PCS amplifier designed using the Infineon/Siemens BFP405 packaged BJT device.

This example demonstrates the impact of implementing a narrow band RF design onto a physical board and the effects of that implementation on the circuit performance.  The design flow will start with an ideal amp and then add different levels of parasitics and show their effect on the design.    

1. Ideal AMP 1900:

This is the amplifier using ideal elements and meets the design requirements.  Note the DC current for each circuit element is annotated on the schematic. 

2. Physical Parts Amp 1900:

The ideal amp with the actual models for the surface mounted parts substituted for the ideal elements.  Look in the subcircuits to see what parasitics are included in these subcircuits.  Note the drop in the gain on the “Gain Comparison” graph.

3. Physical Line Amp 1900:

The ideal transmission lines (TLIN) are replaced with physical microstrip lines (MLIN) to add the real effects, in addition a number of small capacitors are added to estimate the interconnect capacitance.  These can be tuned with the variable intc (Interconnect Capacitance) to see the effect of very small capacitance interconnects, typical interconnect capacitance ranges from 90-180 fF.  This variable is set in the “Global Definitions“.  Try setting this to 0 to see how much these change the circuit performance. 

4. RF Layout Amp 1900:

The amplifier with a true physical implementation on a 25 mil FR4 board.  Note the layout for the fully completed design.  There is a disabled EXTRACT block in the schematic.  For more accurate results, enable the extract block, and the entire layout (minus the surface-mount components) will be solved using AXIEM.  


This example shows the effects of the small capacitances from interconnects and pads on a narrow band RF circuit.  This exemplifies why all of the details need to be modeled even at very low frequencies due to the changes in circuit Q as a result of small capacitances from board interconnects and pads.

You can see as the interconnect capacitances approach 180 fF, the simulation results converge with the actual physical implementation.  This is about right since a 20 mil by 250 mil interconnect generates 180 fF.  This capacitance value was estimated by using a parallel plate capacitance approximation with 25 mil thick FR4 (Er = 4).   

Schematic - 4_RF_Layout_AMP1900

Schematic Layout - 4_RF_Layout_AMP1900

Graph - Stability K Factor

Graph - Gain Comparison