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Design Notes

Sampling Gate Simulation using APLAC Transient

This project demonstrates how to use the APLAC Transient simulator in the AWR Design Environment to simulate the performance of a Step Recovery Diode (SRD) pulse generator driving a sampling gate. It also demonstrates how the swept variable control is used to vary a specific circuit element parameter and how the tuner is used to access data after simulation. Setting up the APLAC simulation parameters is also demonstrated.

Overview

For highly non-linear and possibly chaotic systems such as SRD pulse generators the capabilities of a transient time domain simulator are needed. All circuit simulators are available in the AWR Design Environment; so that if required, both steady state and transient simulations can be conducted using a single schematic. In this particular project only the transient behavior of the circuit is explored.

Pulse_Generator_and_Sampler

This schematic shows the complete sampling gate circuit, and includes some of the graphs described below, with lines indicating the location of those measurements.

The combination of Rbias and Lbias are used for SRD self bias.

Under high power drive conditions the terminal impedance of the SRD becomes low; this impedance is matched to the 50 Ohm source using the matching components Lmatch1, Lmatch2, Lmatch3, Lmatch4, Cmatch1 and Cmatch2.

The pulse generator consists of the lossy capacitor RCpulse1 and RCpulse2, the pulse inductors and the SRD. The 50 fF capacitor models the stray capacitance. The SRD is modelled using the generic Spice diode model. The charge storage time is defined by the manufacturer's data sheet, as is the saturation current, and the bulk resistance.

At some point during reverse bias phase of the drive voltage, the SRD charge is exhausted; at this point the diode current collapses to nearly zero, which gives rise to a high di/dt through the pulse inductors. The high rate of change in inductor current is responsible for creating a high voltage pulse of short duration. This pulse is used to turn on the sampling diodes. In this project the sampling diodes are pre-biased with a common mode voltage which is used to create the so-called back fire pulse; the width of this pulse giving an indication of the frequency response of the system.

Using the Swept Variable Control (SWPVAR) allows a simple experiment to be set up to determine the performance of the pulse generator with a wide range of pulse inductance. The SWPVAR controls the variable Lpulse which in turn defines the inductance for the two pulse inductors. The inductor values are being swept irregularly from 0.1 to 2 nH using the SWPVAR Swept Variable Control block. After the simulation is completed for all swept parameter values, bring up the Tuner to tune through already simulated data. The tuner shows the sweep index, and the graphs show the value of Lpulse for the displayed results. This is a handy way to sort large datasets as it often makes a very complicated graph to show all the results on one display. This sort of tuning is set up in the individual measurements. This is different than "Simulation Tuning" which is setup on the schematic and actually causes simulations to run with each parameter change.

Steady State SRD Pulses

This graph shows the pulses generated by the SRD. Using two markers one can see that the approximate 50% pulse width is 59pS when Lpulse=1nH.

Steady State Backfire

This graph shows the backfire pulse at the input to the sampling gate. Using two markers one can see that the approximate 50% pulse width is 19pS, when Lpulse=1nH.

Startup SRD Pulse Behaviour

This graph shows the first five SRD pulses. Enable Auto limits on the x-axis to see all 50 simulated pulses.

Startup Backfire

This graph shows the first five backfire pulses. Enable Auto limits on the x-axis to see all 50 simulated pulses.

Spectrum of Backfire Pulse

As mentioned above, the width of the backfire pulse is related to the frequency response of the sampling gate. This graph displays the output spectrum, where the frequency response of the sampling gate is more obvious.

The number of harmonics calculated by the voltage spectrum measurement, Vharm, is determined by the number of harmonics specified in APLAC simulator options, and is consistent for transient or harmonic balance simulations. In this project, the frequency of the SRD drive is 500MHz. To calculate the spectrum up to 50GHz, the number of harmonics is set to 100, and Limit harmonic order has been disabled.