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Analog to Digital Converter
This example shows the operation of the VSS ideal ADC block. The ADC is set to M= 4096 levels corresponding to a 12 bit A/D. The offset value of the ADC "OFF," a secondary parameter, is set to -2047.5. The sampling rate of the SINE source is set by the SMPFRQ parameter and is 640 times its frequency. The amplitude of the SINE source varies from -2048 to 2048. An AWGN block is used to add a noise floor of -174dB/Hz. The decimator block is used to set the input sampling frequency of the ADC to 64MHz. Finally, the SCALE block is used to adjust the ADC's output from 0 to 4096.
Note the spurious free dynamic range (SFDR) in the Nyquist bandwidth.
Changing the value of M will generate a corresponding log2(M) bit ADC, and the signal will scale accordingly.
For further information please read the on-line help for each block.