Where To Find This Example
AWR Version 14
This example was named in V14, please see Standard_Cell_Design
AWR Version 13
Select Help > Open Examples... from the menus and type either the example name listed above or one of the keywords below.
Or in Version 13 you can open the project directly from this page using this button.
Using Standard Cells in Analog Office
This project is intended to show the user how standard cells can be used within Analog Office. It should be noted that Analog Office is not intended to be used for multi-million gate digital synthesis but is a high frequency analog design tool which has limited digital capabilities and this use model reflects that.
At the moment Analog Office does not support Verilog so for now you must simulate any digital blocks using the Hspice time domain simulator. This limits the size of circuit to one which can be simulated in a reasonable timeframe. There is no hard limit on circuit size, it is limited only by the time you are prepared to wait for results.
Standard Cells Overview
To use standard cells you need to get both the GDSII layout cells and also the accompanying spice netlists from the foundry.
The netlist is imported by doing the following:
Click on Project > Add Netlist > Import Netlist then select the netlist you wish to import. The netlist will now appear as an element in your sub-circuits library.
You can create a custom symbol for it by using Project > Circuit Symbols > Create New Symbol.
The GDSII is added first clicking on the Layout tab then right clicking on Cell Libraries > Read GDSII Library. Browse to your GDSII cells and click open. You should then see the layout cell added into the Cell Library tree.
The drawn layers in the GDSII should match the existing layers for the pdk. If they do not, say you got the cells from another source, then you can map the layers by double clicking on the .lpf file and opening the model layer mapping section and editing the layer names accordingly there.
If you don't want to simulate the interconnects between cells then that is all you have to do to start design and layout using standard cells. You wont be able to use inets, the inet short checker, or the rat-line checker on these blocks of layout and instead must treat them like an IP block in the larger IC.
If you want to use inets to simulate the interconnects (and utilize their open/short checkers) then you must add pins to the GDSII to assign the correct connectivity. This is done by opening the GDSII cell and then following Draw > Cell Pin and drawing the pins on the appropriate places in the correct layer (usually Metal1). You must also set the port information to the correct type, e.g. artwork line and set the connection layer in this dialogue also to ensure the inet bridge code functions correctly.
If you open a new schematic and now add your sub-circuit, you can link the symbol you created and the layout artwork by editing the element properties and picking the new ones from the available list.
SPI Slave example
The example project provided here is a very simple 3-wire digital interface which can be used to program up an RFIC. It would typically be used to enable/disable various circuit blocks within an IC or to program up DACs which are then used to set bias voltages, break points, temperature slopes etc within an analog IC. In this case we have an 8-bit serial shift register which then writes its information to an 8-bit parallel register which acts as a memory element. The writing process is controlled by a counter which will send a write command every 8 clock cycles.
1) The circuit is powered up. The memory register is automatically reset, setting its outputs to logic 0.
2) Chip Select(CS) is taken high. This resets the counter, sets the remaining registers to a known state and enables the clock signal to pass internally.
3) The counter counts each clock pulse while data is being passed along the serial register.
4) When the counter reaches 8 it sends a write command to parallel write the data held on the serial register into the memory register.
5) CS is taken low. This disables the counter and the internal clock signal while the data is retained in the memory register. CS allows many devices to share the same clock and data lines on a PCB.
This example circuit contains 760 active devices and takes <40 seconds to simulate on an average PC. The design can be expanded very easily by simply adding additional "Byte_with_Memory" blocks and then modifying the counter to trigger at the appropriate new number of clock cycles.
*The standard cells used here were kindly provided by Professor James Stine, Director of the VLSI Computer Architecture Research Group, Oklahoma State University.
Schematic - SPI_Top_Level
Schematic Layout - SPI_Top_Level
Graph - Interface Outputs