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Where To Find This Example

AWR Version 15

Understanding AWR .emz Files

AWR Version 14

Understanding AWR .emz Files

Design Notes

SIMPLE TEST LAB EXAMPLE

This example shows a simple "Test Lab" setup for a single stage amplifier.

Overview

"Test Labs" is a feature name from the EEsof Series IV toolset. The feature allowed users to design in unique ways by simultaneously simulating multiple "Test Benches" to monitor all the different pieces of their circuit at the same time. For instance in a single stage amplifier (such as the one shown in this example) the following items are all viewed simultaneously:

� The front to back s-parameters and noise figure.

� The insertion loss and input / output impedance of the matching networks,

� The input impedance, NFMin, and Gamma Opt (noise) of the active device while terminated with the output matching network

� The output impedance of the active device while it's terminated with the input matching network

� The maximum gain of the device terminated in 50 ohms

Microwave Office is the ideal environment to setup "Test Lab" simulations for a variety of reasons. The biggest is that it is a measurement driven simulation, so it's very easy to control which "Test Bench" simulates and which doesn't - there are no unnecessary simulation resources wasted calculating data which isn't of interest to the end user. Another key factor is that the Microwave Office environment supports "network terminations," which allows one 2-port network to be terminated with another. These terminations make it very easy to setup the simulations mentioned above where the active device is terminated with one thing or another. Lastly, in the Microwave Office environment, the network analyzer ports (as well as any stimulus port) also provide subcircuit connectivity. The implication here is that when the input match is in a subcircuit that's used in the whole circuit, the "Ports" on it allow for measurements to made directly on the circuit itself and for connectivity in higher levels of hierarchy - it's not necessary to have a separate "Test Bench" for each subcircuit!

Simulating and/or tuning this design while looking at the "Amplifier" Schematic shows many of the measurements mentioned above. The parameters being tuned are on the input and output matching networks.

Device Terminated with Input Match Schematic

This schematic contains the active device terminated on it's input (base) with the input matching network. Note that this termination is not done by placing and instance of the input matching network, but with network termination that's reference the input matching network. The network termination is activated by opening the "Port" dialog box (double click on the port), going to the "Port" tab, and choosing network termination.sch:Device_Terminated_With_Input_Match

Device Terminated with Output Match Schematic

This schematic contains the active device terminated on it's output (collector) with the output matching network. Note that this termination is not done by placing and instance of the output matching network, but with network termination that's reference the input matching network. The network termination is activated by opening the "Port" dialog box (double click on the port), going to the "Port" tab, and choosing network termination.sch:Device_Terminated_With_Output_Match

Input Match Schematic

This schematic contains the input matching network. Note that measurements can be made directly on this schematic as it has "Ports," and that it can be used as a subcircuit with the "Ports" providing the connectivity point through hierarchy.

Output Match Schematic

This schematic contains the output matching network. Note that measurements can be made directly on this schematic as it has "Ports," and that it can be used as a subcircuit with the "Ports" providing the connectivity point through hierarchy.

Device Match Schematic

This schematic contains the active device s-parameters. Note that measurements can be made directly on this schematic as it has "Ports," and that it can be used as a subcircuit with the "Ports" providing the connectivity point through hierarchy.

Amplifier Graph

This graph shows S21, S11, and S22 of the entire amplifier (input match, device, and output match). It also shows GMax for just the device.

Device Graph

This graph shows S21, S11, and S22 of the device.

Input Junction Graph

This graph really highlights the benefits of a "Test Lab" setup. It shows optimum noise figure match and the conjugate of S11 of the device terminated with the output matching network. In other words, it shows the impedance that the input match should present to the device for maximum power transfer. They key here is that it's not JUST the impedance of the device terminated into 50 ohms, but the device as it's terminated with the output matching network, exactly what the input match sees in the complete circuit. Also shown is S22 of the input match, or the impedance that it presents to the active device. Lastly, stability circles that show the regions where an input load could cause the output to be unstable are plotted. Close examination of the stability circles reveals that there are two circles for each frequency point, a solid one showing the stable / unstable region border and a dotted one indicating the unstable side of the circle.

Input Match Graph

This graph shows S21, S11, and S22 of the input matching network.

Noise Graph

This graph shows the noise figure of the entire amplifier (input match, device, and output match). It also shows the minimum noise figure for just the device.

Output Junction Graph

This graph really highlights the benefits of a "Test Lab" setup. It the conjugate of S22 of the device terminated with the input matching network. In other words, it shows the impedance that the output match should present to the device for maximum power transfer. They key here is that it's not JUST the impedance of the device terminated into 50 ohms, but the device as it's terminated with the input matching network, exactly what the output match sees in the complete circuit. Also shown is S11 of the output match, or the impedance that it presents to the active device. Lastly, stability circles that show the regions where an output load could cause the input to be unstable are plotted. Close examination of the stability circles reveals that there are two circles for each frequency point, a solid one showing the stable / unstable region border and a dotted one indicating the unstable side of the circle.

Output Match Graph

This graph shows S21, S11, and S22 of the output matching network.gph:Output Match