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Downlink WCDMA Receiver Sensitivity Test:
This project can be used to evaluate the performance of a UE receiver according to ETSI TS 125 101 V6.8.0 (2005-06) Technical Specification. Reference Sensitivity Level Test is defined in Section 7.3 of the document and Demodulation in Static Propagation Conditions is defined in Section 8.2.
For this test, the TX transmits a downlink WCDMA signal source containing a 12.2 kbps DL reference measurement channel, defined in Annex A.3.1. The WCDMA source contains all physical channels used for connection setup (Annex C.2) and during connection (Annex C.3). Since measurements are performed during connection, the physical channels in the WCDMA source are configured according to Annex C.3. The channels that are used during connection setup but not during connection are disabled. The user can enable any of these channels manually by right-clicking on the WCDMA_DL_TSIG subcircuit, selecting Edit Subcircuit, right-clicking on the desired channel and selecting Toggle Enable.
The BER block calculates the bit error rate, while the FER block calculates the block error rate (BLER).
For other conformance tests please refer to the complete set of examples in the Conformance Tests subfolder:
The test may be cofigured by setting appropriate parameters in the Global Definitions window. These parameters, which are boxed for easy access, are:
CarrierFreq_MHz: Carrier Frequency (MHz)
SigLevel_start_dBm: Start Signal Level (dBm)
SigLevel_span_dB: Span of Signal Levels (dB)
SigLevel_step_dB: Step of Signal Levels (dB)
MinNumErrsCollect: Minimum Number of Errors to collect for each signal level
MaxNumBlockRun: Maximum number of blocks to run for each signal level
The parameter Ch_levels in WCDMA UE RXSensPerf system diagram determines the relative power levels of the following channels: SCH, P-CCPCH, P-CPICH, PICH, S-CCPCH, AICH, DPCH, OCNS, HS-SCCH, HS-PDSCH. They are set according to the DL reference measurement channel levels defined in Annex C.3 of the above mentioned specification document.
Two system diagrams are provided for the TX and RX DUT implementations. User can implement their own designs inside these system diagrams.