VSS bus structures allow efficient implementation of parallel designs, s=
uch as phased arrays. The system diagram Reference
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shows a simple 4 element phased array operating in receive mode. Each ar=
ray element path consists of an antenna and an amplifier. The same array ar=
chitecture may be implemented using buses in VSS. This is achieved by doing=
the following:
- Replace PHARRAY_RXSIG with PHARRAY_RXSIG_BUS.
- Components in each array elements are converted to vector instances by=
adding [0:N-1] to their ID parameter, where N is the multiplicity factor, =
or size of the bus. For example, the ID parameter of the ANTENNA block is c=
hanged from S3 to S3[0:3].
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- The COMBINER is replaced with a BUS_SPLITTER.
Using this approach, the implementation of the phased array can be great=
ly simplified. It is worth noting that behind the scenes the bus implementa=
tion is identical to the reference implementation, so there is no performan=
ce improvement associated with it. However, it is much simpler to design su=
ch architectures using buses.
Named connectors may be used to access individual elements in a bus. To =
do this, an NCONN block should be placed in the system diagram and renamed =
so that it matches the name of the desired bus. By default, the named conne=
ctor will be connected to the first element of the bus. To access other ele=
ments, you can use the syntax B[i] where B is the name of the bus and i is =
the 0-based index of the desired element.
This example contains three measurements that are performed on both, the=
reference and the bus implementation of the phased array. These are noise =
figure (NF), gain over temperature (G/T) and node power. The G/T measuremen=
t is also calculated using output equations. It is easy to see that measure=
ments on both array implementations match.