You can also open the project directly from this page using this button.=
Make sure to select the Help > Enable Guided Help from=
the menus before clicking this button.
Open Install Example
Design Notes
Phase Lock Loop (PLL)
This example demonstrates the use of the VSS PLL blocks.
The two system diagrams "CE PLL System" and "Real PLL System" illustrate=
the fact that a PLL design can be simulated using the signal's complex env=
elope (CE) or the signal itself (real). The data type of the feedback VCO's=
output node determines if the CE or the real signal is used. The VCO's out=
put node color is red for CE and yellow for real.
The center and sampling frequencies around the loops can be verified wit=
h the FRQ_PROP measurements (System/Tools) in the "Propagated Frequency CE"=
and "Propagated Frequency Real" tabular graphs. The annotations CTRFRQ and=
SMPFRQ could also have been used to view the frequencies directly on the s=
ystem diagrams.
The "Control voltage" graph compares the control voltage waveforms of th=
e CE and real simulations. The graph shows the waveforms are similar except=
for a minor difference in phase.
The "Spectrum OUT" graph compares the power spectrums of the output of t=
he VCOs. The graph indicates the spectrums are similar.
The system diagram "CE PLL System" has its sampling frequency set to 5 G=
Hz. This is done by selecting "CE PLL System" in the project tree and then =
choosing "Options" from the pull down menu. Under the "Simulator" tab you w=
ill note that this project has its sampling frequency set to 5 GHz and it d=
oes not utilize the "Default System Options" settings, which set the sampli=
ng frequency to 10 GHz. The system diagram "Real PLL System" uses the defau=
lt system options settings.
The advantage of running in CE mode is a reduction in simulation time, i=
n exchange for the somewhat reduced accuracy that comes with lower sampling=
rates. For example, issues like the discretization of the loop filter (via=
bilinear transform, see the online help for 2ND_PASS) or the accuracy of p=
rediction of zero-crossings have a lot to do with the selection of sampling=
frequency, with more accurate results for higher sampling frequency. Of co=
urse, issues like simulation time or resolution bandwidth in spectrum plots=
then become important, so usually a compromise is sought. The availability=
of the CE mode of running a PLL makes finding this compromise easier.
The "Real PLL System" uses a sampling frequency of 10GHz and takes longe=
r to run than the CE system.
In both system diagrams a 225 MHz reference oscillator is used with a di=
vide ratio of 4, forcing the VCO to stabilize at 4 x 225 =3D 900 MHz. The 1=
0 GHz and 5 GHz sampling frequencies of the real and CE systems, respective=
ly, have been chosen to illustrate the fact that the sampling frequency doe=
s not need to be an exact multiple of any particular frequency in the syste=
m, including both the VCO output and the reference frequencies.
Running the PLL simulation in real mode allows you to monitor the result=
ing time domain waveforms before and after the DIVIDER block. As expected t=
he output of the divider (the black waveform) has a 4.44ns period, correspo=
nding to its frequency of 225 MHz =3D 900/4 MHz. You can also monitor simil=
ar waveforms in CE mode by using the CE2R block found in Converters / Compl=
ex Envelope to convert the complex envelope signals to the equivalent real =
signals then viewing those waveforms.
Note that the current from the charge-pump (CP) is never identically zer=
o, even during lock, as the delay of the resetting feedback NAND gate insid=
e the PFDCP block (see the online help for the block) causes pulses of very=
small duration (hence small amplitude in our sampled environment) to appea=
r even when the two inputs of the PFDCP are in perfect lock.
Additional Note 1: Sampling Frequency:
For purposes of illustration try setting the sampling frequency of both =
system diagrams to 1 GHz. Note that in CE mode the PLL will still "lock", a=
nd that the resulting spectrum is similar to the previous spectrum. This is=
because narrowband CE signals around the center frequency are enough to in=
clude the basic waveform information. However, the PLL simulation in real m=
ode does not have a high enough sampling frequency to resolve the 900 MHz s=
ignal and the results are meaningless.
Additional Note 2: DIVIDER (Real mode):
The division ratio of the divider block (DIVIDER) is controlled by the i=
nput connected to node 2. In this case, a SRC_R is used to set the division=
ratio to 4. If input node 2 is left disconnected then the DIVIDER's N para=
meter sets the ratio.
A fractional-N PLL can be simulated by using the DIVIDER's input node 2.=
Only integer control values can be used.
If the division ratio is 1, the output of the divider just repeats the i=
nput, no squaring is performed.
The output of the divider has a duty cycle dependent on the division rat=
io. The output waveform goes to +Vp at the first Upward-Zero-Crossing (UZC)=
and goes back down to -Vp at the second. To obtain a 50% duty cycle, you w=
ould need to end a chain of dividers with a divide-by-2 (N=3D2).
The output waveform of the divider can (and does) exceed +/-Vp at the cr=
ossing points so that the location of the zero-crossing can be preserved fo=
r the PFDCP that follows. The plot "DIV WVFM" needs to be manually scaled f=
or this reason.
Additional Note 3: DIVIDER (CE mode):
Please note that the output of the VCO is a red triangle, to indicate CE=
.
Unlike in real mode, the division ratio in complex mode can be fractiona=
l, both as parameter N (inside DIVIDER) and as set by input node 2.
The parameter N divides the center frequency of the input.
For more information on the blocks used in the system diagrams please re=
ad the online help for those blocks.
System Diagram - C=
E PLL System
System Diagram -=
Real PLL System
Graph - Spectrum OUT <=
span class=3D"confluence-embedded-file-wrapper">
Graph - DIV WVFM
Graph - Control voltage=
Graph - CP current