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Where To Find This Example

AWR Version 14

Select Help > Open Examples... from the menus and type either the example name listed above or one of the keywords below.

Or in Version 14 or higher you can open the project directly from this page using this button. Make sure to select the Enable Guided Help before clicking this button.

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AWR Version 13

This example was renamed since the previous version. Please see Previous Example Page for the version 13 page.

Design Notes

Using Standard Cells in Analog Office

This project is intended to show the user how standard cells can be used within Analog Office.   It should be noted that Analog Office is not intended to be used for multi-million gate digital synthesis but is a high frequency analog design tool which has limited digital capabilities and this use model reflects that.  

At the moment Analog Office does not support Verilog so for now you must simulate any digital blocks using the Hspice APLAC time domain simulator.   This limits the size of circuit to one which can be simulated in a reasonable timeframe.   There is no hard limit on circuit size, it is limited only by the time you are prepared to wait for results.

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To use standard cells you need to get both the GDSII layout cells and also the accompanying spice netlists from the foundry.     If these are not already found in the existing PDK then you can augment the RF PDK fairly easily by doing the following.

The netlist is imported by doing the following:

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The GDSII is added first clicking on the Layout tab then right clicking on Cell Libraries > Read GDSII Library.   Browse to your GDSII cells and click open. You should then see the layout cell added into the Cell Library tree.

The drawn layers in the GDSII should match the existing layers for the pdk.   If they do not, say you got the cells from another source, then you can map the layers by double clicking on the .lpffile and opening the model layer mapping section and editing the layer names accordingly there.

If you don't want to simulate the interconnects between cells then that is all you have to do to start design and layout using standard cells.   You won’t won't be able to use inets, the inet short checker, or the rat-line checker on these blocks of layout and instead must treat them like an IP block in the larger IC.

If you want to use inets to simulate the interconnects (and utilize their open/short checkers) then you must add pins to the GDSII to assign the correct connectivity.   This is done by opening the GDSII cell and then following Draw > Cell Pin and drawing the pins on the appropriate places in the correct layer (usually Metal1).   You must also set the port information to the correct type, e.g. artwork line and set the connection layer in this dialogue also to ensure the inet bridge code functions correctly.

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The example project provided here is a very simple 3-wire digital interface which can be used to program up an RFIC.   It would typically be used to enable/disable various circuit blocks within an IC or to program up DACs which are then used to set bias voltages, break points, temperature slopes etc within an analog IC.   In this case we have an 8-bit serial shift register which then writes its information to an 8-bit parallel register which acts as a memory element.    The writing process is controlled by a counter which will send a write command every 8 clock cycles.

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1) The circuit is powered up.   The memory register is automatically reset, setting its outputs to logic 0.

2) Chip Select(CS) is taken high.   This resets the counter, sets the remaining registers to a known state and enables the clock signal to pass internally.

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4) When the counter reaches 8 it sends a write command to parallel write the data held on the serial register into the memory register.

5) CS is taken low.   This disables the counter and the internal clock signal while the data is retained in the memory register.   CS allows many devices to share the same clock and data lines on a PCB.

This simple example circuit contains 760 active devices and takes <40 seconds to simulate on an average PC.  The design can be expanded very easily by simply adding additional "Byte_with_Memory" blocks and then modifying the counter to trigger at after the appropriate new number of clock cycles.  

*The standard cells used here were kindly provided by Professor James Stine, Director of the VLSI Computer Architecture Research Group, Oklahoma State University.

Schematic - Aplac_SPI_Top_Level

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Schematic

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AP_Counter

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Schematic - AP_Buffer

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Graph - Interface Outputs

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