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Where To Find This Example

AWR Version 14

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AWR Version 13

This example was renamed since the previous version. Please see Previous Example Page for the version 13 page.

Design Notes

Quarter-Wave Transformer with AXIEM Extraction and Optimization


AXIEM is a mesh efficient solver, and simulations of very large structures are fast enough for EM optimization.   In this example, schematic elements are used to construct layout that is extraced to an AXIEM EM structure that provides an accurate electrical model.   In addition to speed, another advantage of AXIEM is that it is an open boundary solver. For simulation of of large sturctures, such as this dual stage quarter-wave transformer (half-wavelenth long), AXIEM does not have box resonances that can occur for electrically large structures using a gridded solver such as EMSight.


"TwoStageQuarterWaveTransformer_4p" schematic is constructed from standard microstrip elements.   Notice that the construction of the mode suppression gaps in the first transformer stage is created using the M3CLIN, MBENDRWX, MCROSS, and MLIN elements in order to create correct layout.   MTEE.TL2 and MTEE.TL7 are used only to match the gap width and most probably would never be used in this way for an accurate electrical model of the structure.   Certainly many of these elements are being used in a manner that either invalidates their distributed electrical model or is out of the models validity range.   The schematic elements are only being used for their layout during extraction which is valid since AXIEM will provide the correct electrical model for the entire structure.

To extract the layout, Right-Click the EXTRACT block in the "TwoStageQuarterWaveTransformer_4p" schematic and select Toggle Enable. Then Right-Click the EXTRACT block again and select Add Extraction generate the "AXIEM_Extract_Doc" EM structure.   With the EXTRACT block enabled, "AXIEM_Extract_Doc" simulation results are used in place of the circuit models in the "TwoStageQuarterWaveTransformer_4p" schematic.   With the EXTRACT block disabled, circuit models are used.

Important Points:

1)    The STACKUP needs to be correctly set up for EM extraction

2)    The EXTRACT Block needs to have Hierarchy set to "On" if the schematic and AXIEM simulations are needed at higher levels of a circuit


"Test_Xformer_2p" schematic combines Ports 1, 2, and 3 so that an optimization can be done with their combined impedance to a specified load impedance.   That load impedance can be put directly into the impedance of Port 1 or the optimization goals can be specified in terms of a ZIN() value.   Notice that the schematic symbol for "TwoStageQuarterWaveTransformer" subcircuit was created using the Symbol Generator Wizard, which creates symbols based on layout.   Layout-based symbols makes wiring in at the next level of hierarchy very simple.


The schematic "TwoStageQuarterWaveTransformer" has parameterized elements and is set up so that the layout will properly snap together after any changes in the parameter values.   The optimization parameters in this case are just the lengths and widths of the two sections.   The gap and junction width (Wjunc) are set to constants.   Tuning on the lengths and widths will change the schematic layout in real time and the load point simulation will update as well.   A user can freeze (CTRL-F) the graph and enable the EXTRACT block after tuning and run the extracted EM simulation.  

The enabled parameters on "TwoStageQuarterWaveTransformer_4p" schematic (with EXTRACT block disabled) will simulate a load impedance that is within 1% of 4Ω.   When the EXTRACT block is enabled for EM simulation, the results shift up in impedance to 5.1Ω.    Choose Simulate > Optimize > Start to begin the optimization of impedance within bounds of 3.9 to 4.1 Ω real and -0.1 to 0.1 Ω imaginary. The Discrete Local Search optimizer is ideal for EM optimization since each optimization step will be on a user defined step size.   

Simulation Plots

The impedance looking into the "Test_Xformer_2p" schematic is plotted on both the Smith Chart and on a table to see the ZIN() at Port 1.