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AWR Version 14

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AWR Version 13

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Design Notes

Phased Array Implementation with Bus Structures

VSS bus structures allow efficient implementation of parallel designs, such as phased arrays. The system diagram Reference

shows a simple 4 element phased array operating in receive mode. Each array element path consists of an antenna and an amplifier. The same array architecture may be implemented using buses in VSS. This is achieved by doing the following:


- Components in each array elements are converted to vector instances by adding [0:N-1] to their ID parameter, where N is the multiplicity factor, or size of the bus. For example, the ID parameter of the ANTENNA block is changed from S3 to S3[0:3]. 

- The COMBINER is replaced with a BUS_SPLITTER.

Using this approach, the implementation of the phased array can be greatly simplified. It is worth noting that behind the scenes the bus implementation is identical to the reference implementation, so there is no performance improvement associated with it. However, it is much simpler to design such architectures using buses.

Named connectors may be used to access individual elements in a bus. To do this, an NCONN block should be placed in the system diagram and renamed so that it matches the name of the desired bus. By default, the named connector will be connected to the first element of the bus. To access other elements, you can use the syntax B[i] where B is the name of the bus and i is the 0-based index of the desired element.

This example contains three measurements that are performed on both, the reference and the bus implementation of the phased array. These are noise figure (NF), gain over temperature (G/T) and node power. The G/T measurement is also calculated using output equations. It is easy to see that measurements on both array implementations match.