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Select Help > Open Examples... from the menus and type either the example name listed above or one of the keywords below.

Or in Version 13 14 or higher you can open the project directly from this page using this button. Make sure to select the Enable Guided Help before clicking this button.

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Sampling Gate Simulation using HSpiceAPLAC Transient

This project demonstrates how to use the HSpice capability of APLAC Transient simulator in the AWR Design Environment to simulate the performance of a Step Recovery Diode (SRD) pulse generator driving a sampling gate.    It also demonstrates how the swept variable control is used to vary a specific circuit element parameter and how the tuner is used to access pre-simulated data after simulation.   Setting up the HSpice APLAC simulation parameters is also demonstrated.

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For highly non-linear and possibly chaotic systems such as SRD pulse generators the capabilities of a transient time domain simulator are needed.   This capability of All circuit simulators are available in the AWR Design Environment will allow the user tremendous flexibility in how circuits may be analyzed.  The links to the HSpice transient time domain simulator are to be found within a single design environment; so that if required, both steady state and transient simulations can be conducted using a single schematic.   In this particular project only the transient behaviour behavior of the circuit is explored.

Pulse_Generator_and_Sampler The schematic "Pulse_Generator_and_Sampler"

This schematic shows the complete sampling gate circuit.   The basic building blocks of the sampling gate are as follows., and includes some of the graphs described below, with lines indicating the location of those measurements.

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The combination of Rbias and Lbias are used for SRD self bias.

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The pulse generator consists of the lossy capacitor RCpulse1 and RCpulse2, the pulse inductors and the SRD.   The 50 fF capacitor models the stray capacitance.   The SRD is modelled using the generic Spice diode model.   The charge storage time is defined by the manufacturer’s manufacturer's data sheet, as is the saturation current, and the bulk resistance.

At some point during reverse bias phase of the drive voltage, the SRD charge is exhausted; at this point the diode current collapses to nearly zero, which gives rise to a high di/dt through the pulse inductors.   The high rate of change in inductor current is responsible for creating a high voltage pulse of short duration.   This pulse is used to turn on the sampling diodes.   In this project the sampling diodes are pre-biased with a common mode voltage which is used to create the so-called back fire pulse; the width of this pulse giving an indication of the frequency response of the system.

On the schematic, note that two Using the Swept Variable Control (SWPVAR) allows a simple experiment to be set up to determine the performance of the pulse generator with a wide range of pulse inductance. The SWPVAR controls the variable Lpulse which in turn defines the inductance for the two pulse inductors. The inductor values are being swept irregularly from 0.1 to 2 nH using the SWPVAR Swept Variable Control block.   After the simulation is complete and each completed for all swept parameter has been solvedvalues, bring up the parameter tuner and you will see that you can use the Tuner to tune through already simulated data.   The tuner shows the sweep index, and the graphs show the value of Lpulse for the displayed results. This is a handy way to sort large datasets as it often makes a very complicated graph to show all the results out on one display.   This sort of tuning is set up in the individual measurements.   This is different than "Simulation Tuning" which is setup on the schematic and actually causes simulations to run with each parameter change.

Steady State SRD Pulses Graph

The This graph “SRD Pulses” shows the pulses generated by the SRD.   Using two markers one can see that the approximate 50% pulse width is 51pS59pS when Lpulse=1nH.

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Steady State Backfire Graph

The This graph "Backfire" shows the backfire pulse at the input to the sampling gate.   Using two markers one can see that the approximate 50% pulse width is 19pS, when Lpulse=1nH. Initial

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Startup SRD Pulse Behaviour

The This graph “Initial SRD Pulse Behaviour” shows the first fifty five SRD pulses. Enable Auto limits on the x-axis to see all 50 simulated pulses.

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Startup Backfire

This graph shows the first five backfire pulses. Enable Auto limits on the x-axis to see all 50 simulated pulses.

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Spectrum of Backfire Pulse Train

As mentioned above, the width of the backfire pulse is related to the frequency response of the sampling gate.   The graph “Spectrum of Backfire Pulse”, This graph displays the output spectrum, where the frequency response of the sampling gate .  Because the behavior of the circuit can be computed using both the Harmonic Balance simulator and the transient domain simulator, the frequency specification used to define the frequency range of the spectral analysis is controlled is more obvious.

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The number of harmonics calculated by the voltage spectrum measurement, Vharm, is determined by the number of harmonics employed by the Harmonic Balance simulator.  To calculate the spectrum up to 50GHz, the following settings have been made.  These settings are found as follows, Right-click "Pulse_Generator_and_Sampler" schematic in the project browser and choose Options.  In the Options dialog window click the Harmonic Balance tab.  In specified in APLAC simulator options, and is consistent for transient or harmonic balance simulations. In this project, the frequency of the SRD drive is 500MHz, thus to calculate a spectrum . To calculate the spectrum up to 50GHz, the number of harmonics is set to 100.  Uncheck , and Limit harmonic order.

HSpice Settings

The HSpice settings are available from the Options dialog window under the Transient Options tab.  In place of using the default time defined by the Harmonic Balance settings, this schematic uses a start time of 0 Secs, a stop time of 100 nSecs and a step of 0.005 nSec (5 pSecs). 

Swept Variable Control

Using the Swept Variable Control (SWPVAR) allows a simple experiment to be set up to determine the performance of the pulse generator with a wide range of pulse inductance.  The SWPVAR controls the variable Lpulse which in turn defines the inductance for the two pulse inductors.  The SWPVAR symbol is found under Simulation Control in the Circuit Elements browser.

Schematic - Pulse_Generator_and_Sampler

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Graph - Spectrum of Backfire Pulse

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Graph - SRD Pulses

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