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**Device Line Oscillator Design**

This project illustrates the design of a FET oscillator in a common-gate configuration using the “device line method”. The device line method is one of several oscillator design techniques.

This project has been designed using hierarchy. The core circuitry are implemented as subcircuits and then all simulations are preformed at one level up in hierarchy. This is sometimes referred to as a test bench approach. This approach is ideal because there is only one instance of the design blocks, so one change to the circuitry will change the results of all steps of the design.

__Overview__

In this project, we demonstrate a common oscillator design methodology called the “device line method”. The technique is illustrated by designing a FET oscillator in the common-gate configuration. The discussion is broken up into five steps.

The first step is to construct the basic circuit topology of the FET oscillator and determine the unloaded port impedance characteristics using linear simulation. The tuning elements are adjusted until the desired negative resistance port impedance is obtained. The oscillator is designed to drive a 100 Ohm load.

The second step is to estimate the power expected from the oscillator. This is accomplished by carefully injecting a small amount of power into the oscillator at the expected oscillation frequency, and seeing how much power is generated. This is accomplished using a nonlinear harmonic balance power simulation.

The third step is to finish the design of the oscillator by placing a proper matching network at the output port so that a 100 Ohm load can be driven.

The fourth step is to characterize the completed oscillator.

The fifth and final step is to confirm the design using a harmonic balance simulation with the OSCAPROBE element.

__Step 1: The Basic FET Oscillator Topology__

The starting schematic is "FET_Negative_Resistance". This is a subcircuit used in all stages of this design. It includes a feedback inductor, named L_FB, in series with the gate of the transistor, an open stub for tuning named Stub_tune connected to the source terminal of the FET, and a simple port on the drain side. This port will eventually be the output of the oscillator. The port impedance is set to 100 W since that is the approximate real impedance the oscillator is designed to drive. The remaining elements are for biasing the device. Notice a port placed at the gate of the transistor. This is to give a connection location for the OSCAPROBE in the final step of the design. Until that step, port two of this circuit will remain open circuited (unconnected through hierarchy).

The L_FB and the Stub_tune elements are tuned to maximize the input reflection coefficient at 10 GHz. Notice that there is also a quarter wavelength stub, TL4, which shorts out the first harmonic at 20 GHz, in order to give better performance.

The test bench for the first part of the design is called “1_Basic_Topology”. The reflection coefficient is shown in the graph “1 Input Reflection”. The maximum reflection is indeed at 10 GHz. Since the source impedance is 100 Ohms, it is desirable to make the real part of the device impedance to be somewhat more negative than -100 Ohms and have a phase of about 0 at 10 GHz. The input impedance is shown in the graph “1 Input Device Impedance”. The real part of the input impedance is -140 Ohms at 10 GHz; the reactance is small. Therefore, this looks like a reasonable location for the tuning settings.

__Step 2: Determination of the Oscillator’s Output Power__

The next step is to determine the power expected from the oscillator and the proper impedance placed on the input of the device. These values are determined by hooking up the " FET_Negative_Resistance " schematic to a power meter, a resistor, and a Harmonic Balance swept power port. This is shown in "2_FET_Oscillator_Start_Power". The idea is to inject a small amount of power into the oscillator from the input port, PORT_PS1. The oscillator will then produce power, which will be measured by the power meter. The meter also measures the input power, but this is very small compared to the power produced by the oscillator. The 1000 Ohm resistor is used to keep the power injected into the oscillator small, and to ensure convergence of the harmonic balance simulation. The graph “2 Start Power” (included in the schematic) shows that about 14 dBm of power can be produced by the oscillator at 10 GHz.

The graph “2 Start Load Impedance” shows the input impedance at 10 GHz. Note that this is the impedance looking into the oscillator because port 2 of the power meter is attached to the oscillator’s input. The graph shows the impedance of about: -76 - j54 Ohms, when the input power from the port is about 32 dBm, which in turn is where we expect the oscillator’s maximum performance. One can see that the input impedance has changed from the earlier prediction in the previous part, which was a linear simulation.

__Step 3: Creating an Output_Matching Network__

The actual oscillator will run autonomously. It is necessary to create a matching network at the input port, which will present an impedance of: 76 + j54 Ohms to the oscillator. This is necessary to satisfy the steady state oscillator conditions of the load’s impedance being the negative of the oscillator’s input impedance. The matching network is designed using a series and shunt stub, and is shown in the “3_Output_Match” schematic (which is using the “Output_Matching” schematic as a subcircuit).

__Step 4: Final Characterization of the Oscillator__

The completed oscillator is now characterized. The graph "4 Final Power" shows the power sweep from the schematic "4_Large_Signal_Osc". This simulation was stabilized with a shunt resistor due to the impedance transformation of the output matching network. The "4 Final Power" graph shows a peak power of around 14 dBm, the same as the input power. Also, the "4 Final Load Impedance" graph shows the impedance at the power meter. At the drive power where the "4 Final Power" graph saturates (55.5 dBm), the real impedance is nearly 50 ohms and the imaginary impedance is nearly 2 W, showing that the oscillator is well matched at this frequency and power level.

One final analysis is the small signal match of the final oscillator. It should show negative resistance but only in the range where the circuit should be oscillating. The graph "4 Zout" shows that this is the case, the result from the “4 Small Sig Osc” schematic

__Step 5: Check the Design__

As a self check of the device line design technique, the OSCAPROBE has been used to automatically calculate the operating frequency and spectral power of the oscillator. The graph “5 Steady State Power Spectrum” displays the predicted oscillator spectrum. Again, the window in window feature is used to display this graph in the schematic “5_Steady_State_Checks_Using_the_OSCAPROBE”. The calculated delivered power and the frequency of operation show good agreement with the previous steps of the Device Line method. Small adjustments to the circuit can now be made, with the OSCAPROBE used to automate the steady-state power and frequency calculations.