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Design Notes

WiMax Amp with Simulation Filters

This example shows the design and simulation of a Eudyna 10W GaN HEMT amplifier, EGN010MK, utilizing Simulation Filters. User folders are used to organize common measurements typical of amplifier characterization during a design cycle. Simulation filters are a mechanism that allows designers to control which documents are included in the simulation. Filters can be created from simulator, simulation type, and document name. This type of control avoids lengthy simulations of existing documents that do not need to be simulated again in large design projects.

Simulation Filter Overview

- Simulation Filters can be accessed from the Project tree or by choosing Simulate > Manage Simulation Filters from the menu and Switch Lists can accessed from the Project tree or by choosing Simulate > Manage Switch Lists from the menu.

- Users can add as many filters as desired. This is done using the New button. Filters can also be Deleted, Renamed, or Copied (and given a new name).

- The filters themselves can control simulation based on several different fields as described below:

- Document Name - These are all the documents that could be data sources for Measurements in the project (Data Files, Circuit Schematics, and EM Structures). A given Simulation Filter can filter on one or more documents.

- Simulators - These are a broad sorting of different simulation types. Each includes multiple simulation engines. For example, Linear includes the Default Linear simulator, Linearized Harmonic Balance, etc. Nonlinear includes the Default Harmonic Balance, Aplac Harmonic Balance, HSPICE, SPECTRE, etc. DC includes the Default DC engine, HSPICE DC, SPECTRE DC, etc.

- Simulator Type - These are different simulators available for use with Measurements. "Default" indicates the AWR supplied Linear, Harmonic Balance, and DC engines.

- Switch Lists - These include any Switch Lists that are defined in the project.

A checkbox next to a field indicates that any Measurements, Optimization Goals, Yield Goals, or Output Equations that match the criteria will simulate.

An example would be to setup a Simulation Filter that only allows nonlinear simulations using the AWR Harmonic Balance engine. To do this, a new filter would be created and, for that filter, the box next to Linear and DC Simulation Types would be unchecked, while the box next to Nonlinear would be checked. At this point, the filter will only allow nonlinear simulations, but isn't restricted to the AWR Harmonic Balance engine. HSPICE or SPECTRE would also still simulate. So, the box next to All Simulators would be unchecked and the box next to Default would be checked. Default means the AWR Linear, Harmonic Balance, and DC engines. With both of these changes made on this same filter, the end result is that only measurements requiring nonlinear simulations using the AWR Harmonic Balance engine will run.

Simulation Filters in This Project

- Evaluation Board Small Signal - Only measurements pointed to the Evaluation_Board_Small_Signal_Test schematic will simulate.

- Evaluation Board 1 Tone - Only measurements pointed to the Evaluation_Board_Power_Test schematic will simulate.

- Evaluation Baord 2 Tone - Only Measurements pointed to the Evaluation_Board_2_Tone Test schematic will simulate.

- Simulation Harmonic Balance - Only Harmonic Balance simulation will run.

- Simulation DC - Only DC simulation will run.

- Simulation Linear - Only linear simulation will run.

When this project is first opened, only the Evaluation Board Small Signal filter is active. So, pressing the Simulate button will only cause measurements, optimization goals, yield goals, and output equations that point to the Evaluation Board Small Signal Test to simulate. The effect of other simulation filters can be seen by turning them on or off. Note that multiple simulation filters can be turned on simultaneously.

Project Overview

This project takes a step-by-step approach to the design of a WiMAX power amplifier - starting with device characterization, and ending with evaluation circuit measurements.

DC Test

This folder contains the IV Curve Test Bench schematic which uses the IVCURVE measurement element to sweep the drain from 0 to 100V and step the gate from -2 to 0V. The curves are displayed on the graph titled IV Curves located in the IV Curves folder. Based on the IV curves, we can determine the approximate gate voltage required to bias the device at 50V VDS and 100mA IDS quiescent (per Eudyna's data sheet recommendations).

Device S-Parameters

This folder contains a test bench for measuring the s-parameters of the device. Circuit annotations were used to ensure proper biasing of the device model. The gate voltage was tuned using the Variable Tuner to achieve 100mA of drain current. The graphical results of the s-parameter test are located in the Device S_Parameters folder, and are displayed in both rectangular and Smith Chart format. You can see from these measurements that the input of the device is very close to 50 Ohms at 3.5 GHz.

Device Power Sweep

This folder contains a power sweep test bench. This schematic is almost identical to the s-parameter test bench, one difference being that the output bias tee is replaced by the LTUNER2 element which serves as a tuner and a bias tee. The other difference is that port 1 is now a single-tone power sweep port ranging from 3 to 33 dBm in 1 dB steps. No tuner was needed for the input match, given the device alone is very close to 50 Ohms across the band of interest.

The results of the power sweep are shown in the graph Output Power and Gain vs Input Power located in the "Tuned Power Sweep folder. The linear gain is almost 15 dB and P-3dB is 41.4 dBm.

Evaluation Board S-parameters

Using the information acquired during the device characterization portion of this project, we can create input and output matching networks for this device. The input match is simply a 50-Ohm trace with a blocking capacitor and a bias line. The output match uses two low-impedance traces to transform the output impedance of the device to an optimal power match. Optimization goals were also used to fine-tune the schematic to achieve sufficient gain and flatness across the band of interest.

The small signal results are plotted in the graph titled Test Circuit Small Signal, located in the Test Circuit Results folder. The layouts of the respective matching circuits can also be viewed, taking advantage of the direct link between schematic and layout views available in the AWR Design Environment. Arrays of vias were added using the via fill tool to ensure proper grounding of the top side ground connections. Custom GDSII cells were created for Eudyna's MK package and the screws. The GDSII files for the SMT components were provided by ATC and Murata through the use of AWR's XML library.

Evaluation Board Power Sweep

This project folder contains the Evaluation Board Power Test schematic. This schematic is identical to the Evaluation Board Small Signal Test schematic, with the only exception being that port 1 is now a single-tone power sweep port ranging from 10 to 32 dBm. The power sweep results are plotted in the graph titled Test Circuit Power Sweep, located in the Test Circuit Results folder. The graph shows gain, output power, and drain efficiency.

Evaluation Board 2-Tone

This folder contains the Evaluation Board 2_Tone Test schematic. It is identical to the Evaluation Board Power Test schematic; however, the input port is now a 2-tone power sweep port ranging from 13 to 23 dBm. The results of this test bench can be found in the graphs titled Pout and IM3 vs Input Power and Two_Tone Spectrum, both located in the Test Circuit Results folder.

Schematic - Device_S_Parameter_Test_Bench

Schematic Layout - Input_Match

Graph - IV Curves

Graph - Output Power and Gain vs Input Power